FDC37B72X_07 SMSC [SMSC Corporation], FDC37B72X_07 Datasheet - Page 225

• Manufacturer Part Number: FDC37B72X_07
• Description: 128 Pin Enhanced Super I/O Controller with ACPI Support
• Manufacturer: SMSC [SMSC Corporation]

Note 1: nWRITE is controlled by clearing the PDIR bit to "0" in the control register before performing an
Note 2: The number is only valid if nWAIT is active when IOW goes active.
NAME
t10
t11
t12
t13
t16
t17
t18
t19
t20
t21
t1
t2
t3
t4
t5
t6
t8
t9
EPP Write.
nIOW Asserted to PDATA Valid
Command Deasserted to nWRITE Change
nWRITE to Command
nIOW Deasserted to Command Deasserted (Note 2)
Command Deasserted to PDATA Invalid
Time Out
SDATA Valid to nIOW Asserted
nIOW Deasserted to DATA Invalid
nIOW Asserted to IOCHRDY Asserted
nWAIT Deasserted to IOCHRDY Deasserted
IOCHRDY Deasserted to nIOW Deasserted
nIOW Asserted to nWRITE Asserted
PDATA Valid to Command Asserted
Ax Valid to nIOW Asserted
nIOW Deasserted to Ax Invalid
nIOW Deasserted to nIOW or nIOR Asserted
nWAIT Asserted to IOCHRDY Deasserted
Command Deasserted to nWAIT Deasserted
TABLE 94 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE TIMING
DESCRIPTION
226
MIN
100
50
10
10
10
10
40
10
0
0
5
0
0
0
0
TYP
MAX
50
40
35
50
12
24
40
50
35
45
UNITS
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns