FDC37B80X SMSC [SMSC Corporation], FDC37B80X Datasheet - Page 105

• Manufacturer Part Number: FDC37B80X
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

Internal PWRGOOD
An internal PWRGOOD logical control is
included to minimize the effects of pin-state
uncertainty in the host interface as V
and off. When the internal PWRGOOD signal is
“1” (active), V
host interface is active.
PWRGOOD signal is “0” (inactive), V
3.7V, and the FDC37B80x host interface is
inactive; that is, ISA bus reads and writes will
not be decoded.
Register Behavior
Table 44 illustrates the AT and PS/2 (including
Model 30) configuration registers available and
the type of access permitted.
maintain software transparency, access to all
the registers must be maintained. As Table 44
shows, two sets of registers are distinguished
based on whether their access results in the part
remaining in powerdown state or exiting it.
Access to all other registers is possible without
awakening the part.
accessed during powerdown without changing
the status of the part.
registers will reflect the true status as shown in
the register description in the FDC description. A
write to the part will result in the part retaining
the data and subsequently reflecting it when the
part awakens.
powerdown may cause an increase in the power
consumption by the part. The part will revert
back to its low power mode when the access
has been completed.
PLL CONTROL
(CR24.1)
cc
1
0
0
0
0
is > 3.7V, and the FDC37B80x
Accessing the part during
TABLE 43 - FDC37B80x PLL CONTROLS AND SELECTS
These registers can be
PME POWER
A read from these
When the internal
(CR22.7)
X
0
0
1
1
In order to
cc
cycles on
cc
is
PWRGOOD
INTERNAL
105
X
0
1
0
1
The FDC37B80x device pins nPME, KDAT,
MDAT, IRRX, nRI1, nRI2 and RXD2 are part of
the PME interface and remain active when the
internal PWRGOOD signal has gone inactive,
provided V
Note: If V
wake-up events when V
be at its full minimum potential at least 10 s
before V
and V
difference between the two supplies must not
exceed 500mV.
Pin Behavior
The FDC37B80x is specifically designed for
systems in which power conservation is a
primary concern. This makes the behavior of
the pins during powerdown very important.
The pins of the FDC37B80x can be divided into
two major categories: system interface and
floppy disk drive interface. The floppy disk drive
pins are disabled so that no power will be drawn
through the part as a result of any voltage
applied to the pin within the part's power supply
range. Most of the system interface pins are left
active to monitor system accesses that may
wake up the part.
System Interface Pins
Table 45 gives the state of the system interface
pins in the powerdown state. Pins unaffected by
the powerdown are labeled "Unchanged". Input
pins are "Disabled" to prevent them from
causing currents internal to the FDC37B80x
when they have indeterminate input values.
14 MHz PLL Powered Down
Reserved
14MHz PLL Powered, Selected.
Reserved
Reserved
cc
cc
TR
TR
begins a power-on cycle. When V
are fully powered, the potential
is powered.
is to be used for programmable
DESCRIPTION
CC
is removed, V
TR
must
TR