FDC37B80X SMSC [SMSC Corporation], FDC37B80X Datasheet - Page 141

• Manufacturer Part Number: FDC37B80X
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

Note 3: This chip uses ISA address bits [A11:A0] to decode the base address of each of its logical
Note:
Note:
Note:
Note:
Interrupt
Request Level
Select 0
Default = 0x00
on Vcc POR or
Reset_Drv
LOGICAL
NUMBER
DEVICE
0x09
NAME
And by setting the OUT2 bit in the UART's Modem Control (MCR) Register.
nSMI must be disabled to use IRQ2.
devices.
An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero
value AND :
IRQ pins must tri-state if not used/selected by any Logical Device. Refer to Note A.
All IRQ’s are available in Serial IRQ mode. Only IRQ[3:7] and IRQ[10:12] are available in
Parallel IRQ mode.
LOGICAL
Reserved
DEVICE
For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
For the PP logical device by setting IRQE, bit D4 of the Control Port and in addition
For the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr.
For the Serial Port logical device by setting any combination of bits D0-D3 in the IER
For the RTC by (refer to the RTC section of this spec).
For the KYBD by (refer to the KYBD controller section of this spec).
Table 56 - I/O Base Address Configuration Register Description
Table 57 - Interrupt Select Configuration Register Description
0x70 (R/W)
REG INDEX
REGISTER
INDEX
Bits[3:0] selects which interrupt level is used for
Interrupt 0.
Note: All interrupts are edge high (except ECP/EPP)
Note: nSMI is active low
0x00= no interrupt selected
0x01= IRQ1
0x02= IRQ2/nSMI
0x03= IRQ3
0x04= IRQ4
0x05= IRQ5
0x06= IRQ6
0x07= IRQ7
0x08= IRQ8
0x09= IRQ9
0x0A= IRQ10
0x0B= IRQ11
0x0C= IRQ12
0x0D= IRQ13
0x0E= IRQ14
0x0F= IRQ15
BASE I/O
141
(NOTE3)
RANGE
DEFINITION
BASE OFFSETS
FIXED
STATE
C