FDC37B80X SMSC [SMSC Corporation], FDC37B80X Datasheet - Page 142

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FDC37B80X

Manufacturer Part Number
FDC37B80X
Description
PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
Manufacturer
SMSC [SMSC Corporation]
Datasheet
Note:
Note:
DMA Channel
Select
Default = 0x04
on Vcc POR or
Reset_Drv
NAME
A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND :
For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
For the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr.
For the UART 2 logical device, by setting the DMA Enable bit.
specification.
DMAREQ pins must tri-state if not used/selected by any Logical Device. Refer to Note A.
Table 58 - DMA Channel Select Configuration Register Description
REG INDEX
0x74 (R/W)
Bits[2:0] select the DMA Channel.
0x00= Reserved
0x01= DMA1
0x02= DMA2
0x03= DMA3
0x04-0x07= No DMA active
142
DEFINITION
Refer to the IrCC
STATE
C

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