MC68HC908AP64_07 FREESCALE [Freescale Semiconductor, Inc], MC68HC908AP64_07 Datasheet - Page 39

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MC68HC908AP64_07

Manufacturer Part Number
MC68HC908AP64_07
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
#
Freescale Semiconductor
$FE0A
$FE0B
$FE0C
$FE0D
$FE0E
$FFCF
$FE06
$FE07
$FE08
$FE09
$FE0F
$FFFF
Addr.
MOR is a non-volatile FLASH register; write by programming.
LVI Status Register (LVISR)
Interrupt Status Register 3
Break Status and Control
FLASH Control Register
Register Name
COP Control Register
Mask Option Register
FLASH Block Protect
U = Unaffected
Break Address
Break Address
Register High
Register Low
(BRKSCR)
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 9)
(COPCTL)
Reserved
Reserved
Reserved
(FLBPR)
Register
Register
(BRKH)
(MOR)
(FLCR)
(BRKL)
(INT3)
#
Erased:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Reset:
Read:
Write:
X = Indeterminate
OSCSEL1 OSCSEL0
MC68HC908AP Family Data Sheet, Rev. 4
LVIOUT
BRKE
BPR7
Bit 15
Bit 7
Bit 7
R
R
R
R
U
0
0
0
0
0
0
0
0
0
1
BRKA
BPR6
IF21
14
R
R
R
R
U
6
0
0
0
0
0
6
0
0
0
1
0
BPR5
IF20
13
R
R
R
R
R
U
5
0
0
0
0
0
5
0
0
0
0
0
1
Writing clears COP counter (any value)
Low byte of reset vector
= Unimplemented
Unaffected by reset
BPR4
IF19
12
R
R
R
R
R
U
4
0
0
0
0
0
4
0
0
0
0
0
1
HVEN
BPR3
IF18
11
R
R
R
R
R
U
3
0
0
0
0
3
0
0
0
0
0
1
MASS
BPR2
IF17
10
R
R
R
R
R
U
R
2
0
0
0
0
2
0
0
0
0
0
1
= Reserved
ERASE
BPR1
IF16
R
R
R
R
R
U
1
0
0
0
9
0
1
0
0
0
0
0
1
Monitor ROM
BPR0
PGM
Bit 0
IF15
Bit 8
Bit 0
R
R
R
R
R
U
0
0
0
0
0
0
0
0
0
1
39

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