MC68HC908AP64_07 FREESCALE [Freescale Semiconductor, Inc], MC68HC908AP64_07 Datasheet - Page 91

• Manufacturer Part Number: MC68HC908AP64_07
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

6.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
AUTO — Automatic Bandwidth Control Bit
LOCK — Lock Indicator Bit
ACQ — Acquisition Mode Bit
Freescale Semiconductor
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This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual
operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit.
When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK,
is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0
and has no meaning. The write one function of this bit is reserved for test, so this bit must always be
written a 0. Reset clears the LOCK bit.
When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode
or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is
in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is
stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Automatic bandwidth control
0 = Manual bandwidth control
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
1 = Tracking mode
0 = Acquisition mode
Selects automatic or manual (software-controlled) bandwidth control mode
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking mode
Address:
Reset:
Read:
Write:
$0037
AUTO
Figure 6-5. PLL Bandwidth Control Register (PBWCR)
Bit 7
0
=
LOCK
Unimplemented
6
0
MC68HC908AP Family Data Sheet, Rev. 4
ACQ
5
0
4
0
0
R
3
0
0
=
Reserved
2
0
0
1
0
0
Bit 0
R
CGM Registers
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