MC68HC908AS60ACFN FREESCALE [Freescale Semiconductor, Inc], MC68HC908AS60ACFN Datasheet - Page 264

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MC68HC908AS60ACFN

Manufacturer Part Number
MC68HC908AS60ACFN
Description
M68HC08 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Input/Output Ports
DDRG[2:0] — Data Direction Register G Bits
Figure 22-22
When bit DDRGx is a logic 1, reading address $000A reads the PTGx data latch. When bit DDRGx is a
logic 0, reading address $000A reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
264
These read/write bits control port G data direction. Reset clears DDRG[2:0], configuring all port G pins
as inputs.
1 = Corresponding port G pin configured as output
0 = Corresponding port G pin configured as input
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
DDRG
shows the port G I/O logic.
Avoid glitches on port G pins by writing to the port G data register before
changing data direction register G bits from 0 to 1.
Bit
0
1
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
READ DDRG ($000E)
WRITE DDRG ($000E)
WRITE PTG ($000A)
READ PTG ($000A)
PTG
Bit
X
X
Table 22-7. Port G Pin Functions
RESET
Figure 22-22. Port G I/O Circuit
Input, Hi-Z
I/O Pin
Output
Mode
Table 22-7
NOTE
Accesses to DDRG
DDRGx
PTGx
Read/Write
DDRG[2:0]
DDRG[2:0]
summarizes the operation of the port G pins.
PTG[2:0]
Read
Pin
Accesses to PTG
PTG[2:0]
Freescale Semiconductor
PTG[2:0]
Write
PTGx
(1)

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