MC68HC908AS60ACFN FREESCALE [Freescale Semiconductor, Inc], MC68HC908AS60ACFN Datasheet - Page 282

• Manufacturer Part Number: MC68HC908AS60ACFN
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MSCAN Controller (MSCAN08)
23.12 Programmer’s Model of Message Storage
This subsection details the organization of the receive and transmit message buffers and the associated
control registers. For reasons of programmer interface simplification, the receive and transmit message
buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a
13-byte data structure. An additional transmit buffer priority register (TBPR) is defined for the transmit
buffers.
23.12.1 Message Buffer Outline
Figure 23-11
identifiers. The mapping of standard identifiers into the IDR registers is shown in
the 13-byte data structure are undefined out of reset.
23.12.2 Identifier Registers
The identifiers consist of either 11 bits (ID10–ID0) for the standard, or 29 bits (ID28–ID0) for the extended
format. ID10/28 is the most significant bit and is transmitted first on the bus during the arbitration
procedure. The priority of an identifier is defined to be highest for the smallest binary number.
SRR — Substitute Remote Request
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This fixed recessive bit is used only in extended format. It must be set to 1 by the user for transmission
buffers and will be stored as received on the CAN bus for receive buffers.
shows the common 13-byte data structure of receive and transmit buffers for extended
The foreground receive buffer can be read anytime but cannot be written.
The transmit buffers can be read or written anytime.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
1. Where x equals the following:
2. Not applicable for receive buffers
$05xA
$05xB
$05xC
$05xD
$05xE
$05x0
$05x1
$05x2
$05x3
$05x4
$05x5
$05x6
$05x7
$05x8
$05x9
$05xF
Addr
Figure 23-10. Message Buffer Organization
x = 4 for receiver buffer
x = 5 for transmit buffer 1
x = 6 for transmit buffer 2
x = 7 for transmit buffer 3
TRANSMIT BUFFER PRIORITY REGISTER
DATA SEGMENT REGISTER 0
DATA SEGMENT REGISTER 1
DATA SEGMENT REGISTER 2
DATA SEGMENT REGISTER 3
DATA SEGMENT REGISTER 4
DATA SEGMENT REGISTER 5
DATA SEGMENT REGISTER 6
DATA SEGMENT REGISTER 7
DATA LENGTH REGISTER
IDENTIFIER REGISTER 0
IDENTIFIER REGISTER 1
IDENTIFIER REGISTER 2
IDENTIFIER REGISTER 3
NOTE
Register Name
UNUSED
UNUSED
(1)
Figure
Freescale Semiconductor
23-12. All bits of