MC68HC908AS60ACFN FREESCALE [Freescale Semiconductor, Inc], MC68HC908AS60ACFN Datasheet - Page 347

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MC68HC908AS60ACFN

Manufacturer Part Number
MC68HC908AS60ACFN
Description
M68HC08 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Valid Active Logic 1
Valid Active Logic 0
Valid SOF Symbol
Valid BREAK Symbol
Freescale Semiconductor
In
occurs between a and b, the current bit would be considered a logic 1.
In
occurs between b and c, the current bit would be considered a logic 0.
In
occurs between c and d, the current symbol would be considered a valid SOF symbol.
In
symbol will be considered a valid BREAK symbol. A BREAK symbol should be followed by a
start-of-frame (SOF) symbol beginning the next message to be transmitted onto the J1850 bus. See
J1850 Frame Format for BDLC response to BREAK symbols.
Figure
Figure 27-9
Figure 27-9
Figure 27-9
27-10, if the next active-to-passive received transition does not occur until after e, the current
PASSIVE
PASSIVE
PASSIVE
PASSIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
(2), if the active-to-passive received transition beginning the next data bit (or symbol)
(3), if the active-to-passive received transition beginning the next data bit (or symbol)
(4), if the active-to-passive received transition beginning the next data bit (or symbol)
Figure 27-9. J1850 VPW Received Active Symbol Times
64 μs
a
a
128 μs
200 μs
b
b
c
c
d
(1) INVALID ACTIVE BIT
(2) VALID ACTIVE LOGIC 1
(3) VALID ACTIVE LOGIC 0
(4) VALID SOF SYMBOL
BDLC MUX Interface
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