MC68HC908AS60ACFN FREESCALE [Freescale Semiconductor, Inc], MC68HC908AS60ACFN Datasheet - Page 333

• Manufacturer Part Number: MC68HC908AS60ACFN
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

26.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADICLK — ADC Input Clock Register Bit
Freescale Semiconductor
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock.
set to approximately 1 MHz.
ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC
clock. Reset selects CGMXCLK as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the
clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the
clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be
guaranteed. See
1 = Internal bus clock
0 = External clock (CGMXCLK)
Address:
During the conversion process, changing the ADC clock will result in an
incorrect conversion.
Reset:
Read:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
28.1.6 ADC
$003A
ADIV2
Bit 7
0
Figure 26-4. ADC Input Clock Register (ADICLK)
Table 26-2
ADIV2
X = don’t care
0
0
0
0
1
= Unimplemented
ADIV1
Characteristics.
Table 26-2. ADC Clock Divide Ratio
6
0
1 MHz = ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
shows the available clock configurations. The ADC clock should be
ADIV1
0
0
1
1
X
ADIV0
5
0
f
XCLK
ADIV0
NOTE
ADICLK
X
0
1
0
1
or Bus Frequency
4
0
ADIV[2:0]
ADC Input Clock / 16
ADC Input Clock / 2
ADC Input Clock / 4
ADC Input Clock / 8
ADC Input Clock /1
ADC Clock Rate
3
0
0
2
0
0
1
0
0
Bit 0
0
0
I/O Registers
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