MC68HC908QY2 MOTOROLA [Motorola, Inc], MC68HC908QY2 Datasheet - Page 77

• Manufacturer Part Number: MC68HC908QY2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

MOTOROLA
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
PIN LOGIC
Signal Name
Address bus
RESET
BUSCLKX4
BUSCLKX2
PORRST
Data bus
INTERNAL
PULL-UP
IRST
R/W
V
DD
Signal from the power-on reset module to the SIM
Buffered clock from the internal, RC or XTAL oscillator circuit.
The BUSCLKX4 frequency divided by two. This signal is again divided by two in the SIM
to generate the internal bus clocks (bus clock = BUSCLKX4 ÷ 4).
Internal address bus
Internal data bus
Internal reset signal
Read/write signal
SIM RESET STATUS REGISTER
RESET PIN CONTROL
POR CONTROL
STOP/WAIT
CONTROL
CONTROL
AND PRIORITY DECODE
INTERRUPT CONTROL
CLOCK
Table 7-1. Signal Name Conventions
Figure 7-1. SIM Block Diagram
System Integration Module (SIM)
CLOCK GENERATORS
RESET
COUNTER
SIM
2
CONTROL
MASTER
RESET
Description
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
COP CLOCK
BUSCLKX4 (FROM OSCILLATOR)
BUSCLKX2 (FROM OSCILLATOR)
INTERNAL CLOCKS
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
LVI RESET (FROM LVI MODULE)
FORCED MON MODE ENTRY (FROM MENRST MODULE)
INTERRUPT SOURCES
CPU INTERFACE
System Integration Module (SIM)
Introduction
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