MC68HC908QY2 MOTOROLA [Motorola, Inc], MC68HC908QY2 Datasheet - Page 95

• Manufacturer Part Number: MC68HC908QY2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

7.8.2 Stop Mode
MOTOROLA
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
NOTE:
NOTE:
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (BUSCLKX2 and BUSCLKX4) in
stop mode, stopping the CPU and peripherals. Stop recovery time is
selectable using the SSREC bit in the configuration register 1
(CONFIG1). If SSREC is set, stop recovery is reduced from the normal
delay of 4096 BUSCLKX4 cycles down to 32. This is ideal for the internal
oscillator, RC oscillator, and external oscillator options which do not
require long start-up times from stop mode.
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time
the recovery period.
Figure 7-19
To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
ADDRESS BUS
DATA BUS
CPUSTOP
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
R/W
instruction.
System Integration Module (SIM)
shows the stop mode recovery time from interrupt or break
STOP ADDR
Figure 7-18. Stop Mode Entry Timing
Figure 7-18
PREVIOUS DATA
STOP ADDR + 1
shows stop mode entry timing and
NEXT OPCODE
System Integration Module (SIM)
SAME
SAME
Low-Power Modes
SAME
SAME
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