SAA6752HS/V103 PHILIPS [NXP Semiconductors], SAA6752HS/V103 Datasheet - Page 64

• Manufacturer Part Number: SAA6752HS/V103
• Description: MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
2004 Jan 26
SDRAM interface data, address and control timing: pins SD_DQ31 to SD_DQ0, SD_A13 to SD_A0, SD_CAS,
SD_RAS, SD_WE and SD_OE
T
t
t
t
t
t
t
t
t
t
t
t
t
t
Data output interface timing: pins PDO7 to PDO0, PDIDS, PDOSYNC, PDOAV and PDIOCLK
t
t
t
t
t
t
t
t
t
CAS
RCD
RRD
RP
WR
RSC
RAS
RC
power-up
d(C-D)
d(C-A)
su(D)
h(D)
l-o(PDIDS-PDOVAL)
l-o(PDIDS-PDO)
stab(PDO-PDOVAL)
r(PDOVAL-PDO)
h(PDO-PDIOCLK)
su(PDO-PDIOCLK)
i(PDIOCLK)H
i(PDIOCLK)L
stab(PDIOCLK-PDO)
cy
MPEG-2 video and MPEG-audio/AC-3
audio encoder with multiplexer
SYMBOL
cycle time
CAS latency time
row to column delay time
activate to activate delay
time
row precharge time
write recovery time
mode register set cycle
time
row activate time
row cycle time
wait time after power-on
clock to data output
delay
clock to address output
delay
data input set-up time
data input hold time
PDIDS to PDOVAL
low-ohmic time
PDIDS to PDO[7:0]
low-ohmic time
PDO[7:0] data stable to
falling PDOVAL time
rising
PDOVAL to PDO[7:0]
high-impedance time
PDO[7:0] data to
PDIOCLK hold time
PDO[7:0] data to
PDIOCLK set-up time
input PDIOCLK HIGH
time
input PDIOCLK LOW
time
falling input PDIOCLK to
PDO[7:0] data stable
time
PARAMETER
f
C
C
f
C
C
f
DEBI slave mode
DEBI slave mode
DEBI slave mode
DEBI slave mode
DIO master mode;
PDOVAL = 1
DIO master mode;
PDOVAL = 1
DIO slave mode
DIO slave mode
DIO slave mode;
PDOVAL = 1
sys
SD_CLK
SD_CLK
L(SD_CLK)
L(SD_DQn)
L(SD_CLK)
L(SD_An)
CONDITIONS
= 27 MHz
= 108 MHz
= 108 MHz
= 8 pF;
= 15 pF;
= 15 pF;
= 8 pF;
64
500
2.5
2.5
1
2.5
0
0
10
10
10
10
55
55
36
MIN.
9.26
3
3T
2T
3T
2T
2T
6T
8T
515
4.0
4.0
TYP.
cy
cy
cy
cy
cy
cy
cy
5.0
5.0
20
20
58
SAA6752HS
Product specification
MAX.
ns
clock
cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
s