ISD5116 WINBOND [Winbond], ISD5116 Datasheet - Page 17

• Manufacturer Part Number: ISD5116
• Description: Single-Chip Voice Record/Playback Device Up to 16-Minute Duration with Digital Storage Capability
• Manufacturer: WINBOND [Winbond]

The figure above shows the part of the ISD5116 block diagram that is used in Feed Through Mode. The
rest of the chip will be powered down to conserve power. The bold lines highlight the audio paths. Note
that the Microphone to ANA OUT +/– path is differential.
To select this mode, the following control bits must be configured in the ISD5116 configuration registers.
To set up the transmit path:
To set up the receive path:
The status of the rest of the functions in the ISD5116 chip must be defined before the configuration
registers settings are updated:
October 2000
1. Select the FTHRU path through the ANA OUT MUX—Bits AOS0, AOS1 and AOS2 control the
2. Power up the ANA OUT amplifier—Bit AOPD controls the power up state of ANA OUT. This is bit
1. Set up the ANA IN amplifier for the correct gain—Bits AIG0 and AIG1 control the gain settings of
2. Power up the ANA IN amplifier—Bit AIPD controls the power up state of ANA IN. This is bit D13
3. Select the ANA IN path through the OUTPUT MUX—Bits OPS0 and OPS1 control the state of the
4. Power up the Speaker Amplifier—Bits OPA0 and OPA1 control the state of the Speaker and AUX
state of the ANA OUT MUX. These are the D6, D7 and D8 bits respectively of Configuration
Register 0 (CFG0) and they should all be ZERO to select the FTHRU path.
D5 of CFG0 and it should be a ZERO to power up the amplifier.
this amplifier. These are bits D14 and D15 respectively of CFG0. The input level at this pin deter-
mines the setting of this gain stage. The
help determine this setting. In this example, we will assume that the peak signal never goes
above 1 volt p-p single ended. That would enable us to use the 9 dB attenuation setting, or where
D14 is ONE and D15 is ZERO.
of CFG0 and should be a ZERO to power up the amplifier.
OUTPUT MUX. These are bits D3 and D4 respectively of CFG0 and they should be set to the
state where D3 is ONE and D4 is ZERO to select the ANA IN path.
amplifiers. These are bits D1 and D2 respectively of CFG0. They should be set to the state where
D1 is ONE and D2 is ZERO. This powers up the Speaker Amplifier and configures it for its higher
gain setting for use with a piezo speaker element and also powers down the AUX output stage.
ANA IN Amplifier Gain Settings table
on page 25 will
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