ISD5116 WINBOND [Winbond], ISD5116 Datasheet - Page 32

• Manufacturer Part Number: ISD5116
• Description: Single-Chip Voice Record/Playback Device Up to 16-Minute Duration with Digital Storage Capability
• Manufacturer: WINBOND [Winbond]

6 PIN DESCRIPTIONS
6.1 DIGITAL I/O PINS
SCL (Serial Clock Line)
The Serial Clock Line is a bi-directional clock line. It is an open-drain line requiring a pull-up resistor to
Vcc. It is driven by the "master" chips in a system and controls the timing of the data exchanged over the
Serial Data Line.
SDA (Serial Data Line)
2
The Serial Data Line carries the data between devices on the I
C interface. Data must be valid on this
line when the SCL is HIGH. State changes can only take place when the SCL is LOW. This is a bi-
directional line requiring a pull-up resistor to Vcc.
RAC (Row Address Clock)
RAC is an open drain output pin that normally marks the end of a row. At the 8 kHz sample frequency, the
duration of this period is 256 ms. There are 2048 pages of memory in the ISD5116 devices. RAC stays
HIGH for 248 ms and stays LOW for the remaining 8 ms before it reaches the end of the page.
1 R OW
RAC W aveform
During 8 KHz Operation
2 5 6 m se c
T
R AC
8 m se c
T
R AC LO
The RAC pin remains HIGH for 500 µsec and stays LOW for 15.6 µsec under the Message Cueing mode.
Timing Parameters table
See the
on page 39 for RAC timing information at other sample rates. When a
record command is first initiated, the RAC pin remains HIGH for an extra T
period, to load sample
RACLO
and hold circuits internal to the device. The RAC pin can be used for message management techniques.
1 RO W
RAC W aveform
During M essage Cueing
5 0 0 use c
T
R A C
1 5 .6 us
T
R A C LO
October 2000
Page 31