NAND04G-B2D NUMONYX [Numonyx B.V], NAND04G-B2D Datasheet - Page 32

• Manufacturer Part Number: NAND04G-B2D
• Description: 4 Gbit, 8 Gbit, 2112 byte/1056 word page multiplane architecture, 1.8 V or 3 V, NAND Flash memories
• Manufacturer: NUMONYX [Numonyx B.V]

Device operations
6.8
Figure 19. Multiplane block erase
1. The D1h Confirm code is required by the ONFI 1.0 command set. To maintain backward compatibility, the D1h Confirm
6.9
32/69
I/O
RB
code can optionally be ignored, and then the tIEBSY Busy Time does not occur.
Block Erase
Setup Code
60h
Multiplane block erase
The multiplane block erase operation allows the erasure of two blocks in parallel, one in
each plane.
This operation consists of the following three steps (refer to
erase):
1.
2.
If the multiplane block erase fails, an error is signaled on bit SR0 of the Status Register. To
know which page of the two planes failed, the Read Status Enhanced command must be
issued twice, once for each plane (see
Error detection code (EDC)
The EDC (error detection code) is performed automatically during all program operations. It
starts immediately after the device becomes busy.
The EDC detects 1 single bit error per EDC unit. Each EDC unit has a density of 528 bytes
(or 264 words), split into 512 bytes of main area and 16 bytes of spare area (or 256 + 8
words). Refer to
To properly use the EDC, the following conditions apply:
●
●
8 bus cycles are required to set up the Block Erase command and load the addresses
of the blocks to be erased. The setup command followed by the address of the block to
be erased must be issued for each block. t
insertion of first and the second block addresses. As for multiplane page program
operations, the address of the first and second page must be within the first plane (A18
= 0) and second plane (A8 = 1), respectively.
One bus cycle is then required to issue the Multiplane Block Erase Confirm command
and start the P/E/R Controller.
Block Address
Page program operations must be performed on a whole page, or on whole EDC
unit(s).
The modification of the content of an EDC unit using a random data input before the
copy back program, must be performed on the whole EDC unit. It can only be done
once per EDC unit. Any partial modification of the EDC unit results in the corruption of
the on-chip EDCs.
A18 = 0
Inputs
Table 12
Multiplane Block
Erase Code
tIEBSY
D1h
(1)
and
Figure 20
Setup Code
Block Erase
60h
Section
for EDC unit addresses definition.
Block Address
A18 = 1
Inputs
IEBSY
6.12).
busy time is required between the
Confirm
Code
D0h
NAND04G-B2D, NAND08G-BxC
Figure 19: Multiplane block
(Erase Busy time)
tBLBH3
Busy
70h
Read Status
Register
SR0
ai13173b