PSD813F1A-12J STMICROELECTRONICS [STMicroelectronics], PSD813F1A-12J Datasheet - Page 92
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PSD813F1A-12J
Manufacturer Part Number
PSD813F1A-12J
Description
Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.PSD813F1A-12J.pdf
(110 pages)
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PSD813F1
Table 57. WRITE, Erase and Program Timing (5V devices)
Note: 1. Any input used to select an internal PSD function.
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t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
LVLX
AVLX
LXAX
AVWL
SLWL
DVWH
WHDX
WLWH
WHAX1
WHAX2
WHPV
DVMV
AVPV
WLMV
2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data becomes valid.
6. T
WHAX2
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Address Valid to Leading
Edge of WR
CS Valid to Leading Edge of WR
WR Data Setup Time
WR Data Hold Time
WR Pulse Width
Trailing Edge of WR to Address Invalid
Trailing Edge of WR to DPLD Address
Invalid
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
Data Valid to Port Output Valid
Using Macrocell Register
Preset/Clear
Address Input Valid to Address
Output Delay
WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear
is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
Parameter
Conditions
(Notes
(Notes
(Notes
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
3,6
1,3
3,5
3,4
1
1
3
3
3
3
3
3
2
)
)
)
)
)
)
)
)
)
)
)
)
)
Min Max Min Max Min Max
20
15
15
35
35
6
8
5
8
0
-90
30
55
25
55
22
18
18
40
40
8
9
5
9
0
-12
35
60
28
60
28
10
11
20
20
45
45
10
5
0
-15
38
65
30
65
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns