NAND08GAH0A NUMONYX [Numonyx B.V], NAND08GAH0A Datasheet - Page 76

• Manufacturer Part Number: NAND08GAH0A
• Manufacturer: NUMONYX [Numonyx B.V]

Timings
9.1
9.1.1
Figure 13. Identification timing diagram (Card Identification mode)
9.1.2
Figure 14. SET_RCA timing diagram (Card Identification mode)
9.1.3
Figure 15. Command response timing diagram (Data Transfer mode)
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CMD
Command and response timings
Both host command and device response are clocked out with the rising edge of the host
clock.
Card identification and card operation conditions
The Card Identification (CMD2) and Card Operation Conditions (CMD1) commands are
processed in the open-drain mode. The minimum delay between the host command and
device response is N
Figure 13
Assignment of relative card address
The SET_RCA command (CMD 3) is also processed in open-drain mode. The minimum
delay between the host command and device response is N
Figure 14
Data Transfer mode
After an RCA has been assigned to the device, it switches to Data Transfer mode. In this
mode the CMD line is driven with push-pull drivers.
The command is followed by a two Z-bit period to allow direction switching on the bus, and
by P bits pushed up by the responding device.
This timing diagram shown on
CMD1, CMD2, and CMD3.
CMD
CMD
S T
S T
S T
shows the identification timing diagram.
shows the SET_RCA timing diagram.
Host Command
Host Command
Host Command
Content
Content
Content
ID
CRC E Z
clock cycles.
CRC E Z
CRC E Z
Figure 15
Z P
N
N
* * * * * *
N
* * * * * *
CR
ID
ID
Cycles
Cycles
* * * * *
Cycles
applies to all host command responses except for
Z S T
Z S T
P S T
CID or OCR
Response
Content
Response
Content
Content
NAND08GAH0A, NAND16GAH0D
CR
CRC E
CRC E
clock cycles.
Z
Z
AI13196
Z
AI04333
Z
Z
AI04334
Z
Z
Z
Z