M58BW16FB4T3 STMICROELECTRONICS [STMicroelectronics], M58BW16FB4T3 Datasheet - Page 26

• Manufacturer Part Number: M58BW16FB4T3
• Description: 16 or 32 Mbit (x32, Boot Block, Burst) 3.3V supply Flash memories
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Bus operations
3.1.7
3.1.8
Table 6.
1. X = Don’t Care.
2. Data, Manufacturer Code, Device Code, Burst Configuration Register, Standby Status and Block Protection Configuration
26/81
Asynchronous Bus Read
Asynchronous Latch
Controlled Bus Read
Asynchronous Page Read
Asynchronous Bus Write
Asynchronous Latch
Controlled Bus Write
Output Enable, G
Output Disable, GD
Standby
Reset/Power-Down
Register are read using the Asynchronous Bus Read command.
Bus Operation
Standby
When Chip Enable is High, V
enters Standby mode, the power consumption is reduced to the standby level (I
Data Inputs/Outputs pins are placed in the high impedance state regardless of Output
Enable, Write Enable or Output Disable inputs.
The Standby mode can be disabled by setting the Standby Disable bit (M14) of the Burst
Configuration Register to ‘1’ (see
Reset/Power-Down
The memory is in Reset/ Power-Down mode when Reset/Power-Down, RP, is at V
power consumption is reduced to the standby level (I
impedance, independent of the Chip Enable, E, Output Enable, G, Output Disable, GD, or
Write Enable, W, inputs. In this mode the device is write protected and both the Status and
the Burst Configuration Registers are cleared. A recovery time is required when the RP
input goes High.
Asynchronous bus operations
(2)
Address Latch
Read
Address Latch
Write
Step
IH
V
V
V
V
V
V
V
V
V
V
E
X
IH
IL
IL
IL
IL
IL
IL
IL
IL
IL
, and the Program/Erase Controller is idle, the memory
(1)
Table 17: DC
V
V
V
V
V
V
V
V
V
G
X
X
IH
IH
IH
IH
IH
IL
IL
IL
IL
GD
V
V
V
V
V
V
X
X
X
X
X
IH
IH
IH
IH
IH
IL
characteristics).
V
V
V
V
V
V
V
V
V
W
X
X
IH
IH
IH
IH
IH
IH
IL
IL
IL
DD1
V
V
V
V
V
V
V
V
V
V
RP
V
) and the outputs are high
IH
IH
IH
IH
IH
IH
IH
IH
IH
IH
IL
V
V
V
V
V
V
X
X
X
X
X
L
IH
IH
IL
IL
IL
IL
M58BW16F, M58BW32F
A0-Amax
Address
Address
Address
Address
Address
X
X
X
X
X
X
DD1
Data Output
Data Output
Data Output
DQ0-DQ31
Data Input
Data Input
High Z
High Z
High Z
High Z
High Z
High Z
IL
) and the
. The