STTS2002_11 STMICROELECTRONICS [STMicroelectronics], STTS2002_11 Datasheet
STTS2002_11
Related parts for STTS2002_11
STTS2002_11 Summary of contents
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Features ■ 2.3 V memory module temperature sensor with integrated 2 Kb SPD EEPROM ■ Forward compatible with JEDEC TSE 2002a2 and backward compatible with STTS424E02 ■ Operating temperature range: – –40 °C to +125 °C ■ Single supply voltage: ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STTS2002 4.8 SMBus timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STTS2002 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The STTS2002 is targeted for DIMM modules in mobile personal computing platforms (laptops), servers and other industrial applications. The thermal sensor (TS) in the STTS2002 is compliant with the JEDEC specification TSE2002a2, which defines memory module thermal ...
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STTS2002 2 Serial communications The STTS2002 has a simple 2-wire SMBus/I allows the user to access both the 2 Kb serial EEPROM and the data in the temperature register at any time. It communicates via the serial interface with a ...
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Serial communications Figure 1. Logic diagram 1. SDA and EVENT are open drain. Table 1. Signal names Pin Symbol SDA 6 SCL 7 EVENT SDA and ...
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STTS2002 Figure 3. Block diagram 2 Kb SPD EEPROM Standard array (80h - FFh) Software write-protected array (00h - 7Fh Temperature Sensor Logic Control Comparator ADC Capability Register Configuration Register Temperature ...
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Serial communications 2.2 Pin descriptions 2.2.1 A0, A1, A2 A2, A1, and A0 are selectable address pins for the 3 LSBs of the I They can be set to V internally connected to the E2, E1, E0 (chip selects) of ...
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STTS2002 3 Temperature sensor operation The temperature sensor continuously monitors the ambient temperature and updates the temperature data register. Temperature data is latched internally by the device and may be read by software from the bus host at any time. ...
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Temperature sensor operation 2 Figure 4. SMBus/I C write to pointer register 1 SCL SDA 0 Start by Master 2 Figure 5. SMBus/I C write to pointer register, followed by a read data word 1 SCL SDA 0 0 Start ...
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STTS2002 Figure 6. SMBus/I SCL SDA Start by Master SCL (continued) SDA (continued) 2 3.2 SMBus/I C slave sub-address decoding The physical address for the TS is different than that used by the EEPROM. The TS physical address is binary ...
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Temperature sensor operation 2 3.3 SMBus timing consideration In order for this device to be both SMBus- and I each specification. The requirements which enable this device to co-exist with devices on either an SMBus ...
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STTS2002 Table 2. AC characteristics of STTS2002 for SMBus and I Symbol f SMBUS/I SCL t Clock high period HIGH (1) t Clock low period LOW (2) t Clock/data rise time R (2) t Clock/data fall time F t Data ...
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Temperature sensor registers 4 Temperature sensor registers The temperature sensor component is comprised of various user-programmable registers. These registers are required to write their corresponding addresses to the pointer register. They can be accessed by writing to their respective addresses ...
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STTS2002 Table 4. Pointer register format MSB Bit7 Bit6 0 0 Table 5. Pointer register select bits (type, width, and default values Name CAPA CONF ...
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Temperature sensor registers Table 7. Capability register bit definitions Bit Basic capability 0 – Alarm and critical trips turned OFF. – Alarm and critical trips turned ON. Accuracy – Accuracy ±2 °C over the ...
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STTS2002 4.2 Configuration register (read/write) The 16-bit configuration register stores various configuration modes that are used to set up the sensor registers and configure according to application and JEDEC requirements (see Table 8 on page 19 4.2.1 Event thresholds All ...
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Temperature sensor registers Table 9. Configuration register bit definitions Bit Event mode – Comparator output mode (this is the default). 0 – Interrupt mode; when either of the lock bits (bit6 or bit7) is set, this ...
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STTS2002 Table 9. Configuration register bit definitions (continued) Bit Hysteresis enable (see Figure 8 – Hysteresis is disabled (default) – Hysteresis is enabled at 1.5 °C – Hysteresis is enabled at 3 °C 10:9 ...
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Temperature sensor registers 4.2.5 Event output pin functionality The STTS2002 EVENT pin is an open drain output that requires a pull- system motherboard or integrated into the master controller. EVENT has three operating modes, depending on configuration settings ...
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STTS2002 Figure 9. Event output boundary timings T CRIT T UPPER LOWER Comparator Interrupt S/W Int. Clear Critical Note: Table 11. Legend for Note Event output boundary conditions When T A ...
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Temperature sensor registers 4.3 Temperature register (read-only) This 16-bit, read-only register stores the temperature measured by the internal band gap TS as shown inTable then the LSBs (bit 7 to bit 0) are read. The result is the current-sensed temperature. ...
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STTS2002 A 0.25 °C minimum granularity is supported in all registers. Examples of valid settings and interpretation of temperature register bits for 10-bit (0.25 °C) default resolution are provided in Table 13. Table 13. Temperature register coding examples (for 10 ...
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Temperature sensor registers Table 15. Temperature trip point register format Name UPPER LOWER CRITICAL 4.4.1 Alarm window trip The device provides a comparison window ...
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STTS2002 Table 18. Critical temperature register format Sign MSB Bit Bit Bit Bit Bit Bit 2 is LSB for default 10-bit mode critical trip lockout bit (bit 7 of ...
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Temperature sensor registers 4.5 Manufacturer ID register (read-only) The manufacturer’s ID (programmed value 104Ah) in this register is the STMicroelectronics Identification provided by the Peripheral Component Interconnect Special Interest Group (PCiSIG). Table 19. Manufacturer ID register (read-only) Bit15 Bit14 0 ...
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STTS2002 4.7 Temperature resolution register (read/write) With this register a user can program the temperature sensor resolution from 9-12 bits as shown below. The power-on default is always 10 bit (0.25 °C/LSB). The selected resolution is also reflected in bits ...
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SPD EEPROM operation 5 SPD EEPROM operation 5 SPD EEPROM operation The 2 Kb serial EEPROM is able to lock permanently the data in its first half (from location 00h to 7Fh). This feature has been designed specifically ...
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STTS2002 Prior to selecting the memory and issuing instructions, a valid and stable V be applied. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion ...
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SPD EEPROM operation Table 24. Operating modes Mode Current address read Random address read Sequential read Byte write Page write TS write TS read 5.4 Software write protect Software write-protection allows the bottom half of the memory area (addresses 00h ...
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STTS2002 5.4.1 SWP and CWP If the software write-protection has been set with the SWP instruction, it can be cleared again with a CWP instruction. The two instructions (SWP and CWP) have the same format as a byte write instruction, ...
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SPD EEPROM operation 5.5 Write operations Following a start condition the bus master sends a device select code with the RW bit reset to 0. The device acknowledges this, as shown in The device responds to the address byte with ...
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STTS2002 5.5.3 Write cycle polling using ACK During the internal write cycle, the device disconnects itself from the bus and writes a copy of the data from its internal latches to the memory cells. The maximum write time (t shown ...
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SPD EEPROM operation 5.6 Read operations - SPD Read operations are performed independently of whether hardware or software protection has been set. The device has an internal address counter which is incremented each time a byte is read. Figure 14. ...
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STTS2002 5.6.2 Current address read - SPD For the current address read operation, following a start condition, the bus master only sends a device select code with the RW bit set to 1. The device acknowledges this, and outputs the ...
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SPD EEPROM operation Table 26. Acknowledge when reading the write protection (instructions with R/W bit=1) Status Permanently PSWP, SWP or CWP protected Protected with SWP Not protected PSWP, SWP or CWP 5.7 Initial delivery state - SPD The device is ...
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STTS2002 6 Use in a memory module In the Dual In line Memory Module (DIMM) application, the SPD is soldered directly on to the printed circuit module. The three chip enable inputs (A0, A1, A2) must be connected to V ...
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Maximum ratings 7 Maximum ratings Stressing the device above the ratings listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other ...
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STTS2002 8 DC and AC parameters This section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the ...
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DC and AC parameters Table 30. DC/AC characteristics - temperature sensor component with EEPROM (continued) Sym Description Accuracy for corresponding range B-grade 2.3 V ≤ V ≤ 3 Resolution t Conversion time CONV 2 SMBus/I C interface V ...
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STTS2002 9 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...
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Package mechanical data Figure 16. TDFN8 – 8-lead thin dual flat, no-lead ( mm) package outline (DN) Note: JEDEC MO-229, variation WCED-3 proposal Table 31. TDFN8 – 8-lead thin dual flat, no-lead ( mm) ...
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STTS2002 Figure 17. DN package topside marking information (TDFN8) 1. Temperature grade and package B = B-grade, stacked 2 = Minimum operating voltage of 2 0.80 mm TDFN package 2. Device name TSE2 = STTS2002 3. Traceability ...
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Package mechanical data The landing pattern recommendations per the JEDEC proposal for the TDFN package (DN) are shown in Figure The preferred implementation with wide corner pads enhances device centering during assembly, but a narrower option is defined for modules ...
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STTS2002 Table 32 lists variations of landing pattern implementations, ranked as “Preferred” and Minimum Acceptable” based on the JEDEC proposal. Table 32. Parameters for landing pattern - TDFN8 package (DN) Parameter D2 Heat paddle width E2 Heat paddle height E3 ...
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Package mechanical data Figure 19. Carrier tape for TDFN8 package T TOP COVER TAPE K 0 Table 33. Carrier tape dimensions TDFN8 package Package 8.00 1.50 1.75 +0.30 TDFN8 +0.10/ ±0.10 –0.10 –0.00 48/ ...
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STTS2002 Figure 20. Reel schematic D A Full radius Table 34. Reel dimensions for 8 mm carrier tape - TDFN8 package A B (max) (min) 180 mm 1.5 mm (7-inch) Note: The dimensions given in parameters. 40mm min. Access hole ...
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Part numbering 10 Part numbering Table 35. Ordering information scheme Example: Device STTS2002 Accuracy grade B: Maximum accuracy 75 ° °C = ± 1 °C Voltage 3.6 V Package DN = TDFN8 Temperature ...
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STTS2002 11 Revision history Table 36. Document revision history Date 11-Feb-2009 08-Oct-2009 19-Oct-2009 13-Sep-2010 21-Mar-2011 Revision 1 Initial release. Updated Features, Section Section 3.3, Section Section 5.5.2, Section 12, 13, 24, 25, 28, 29, and 30; ...
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Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any ...