IP200 ETC [List of Unclassifed Manufacturers], IP200 Datasheet - Page 12

• Manufacturer Part Number: IP200
• Description: Interpolation Circuit for Incremental Measuring Systems
• Manufacturer: ETC [List of Unclassifed Manufacturers]

Each transfer process is triggered by the sending of a command. To this effect, SEN is kept low during 16
SCLK clock cycles. The input data at SDI is evaluated a the rising edge of SCLK. At the same time, the
shifting of the data of the hold register is triggered at every rising edge at SCLK.
Figure 7
5.2.2
1)
2)
Command word examples
SPI-Access:
SCLK
SEN
SDI
SDO
t
t
t
t
t
t
t
Bit No. at signal SDI
15
0
0
0
0
1
1
1
Bit
nB
H(3:0)
A(7:0)
C(7:0)
D(7:0)
H
L
w
RDY
VDI
SETDI
VDO
bit must be set to zero in single-channel systems
command load the internal data into a 32-bit hold register
Name
D-09116 Chemnitz, Germany
Load bit 15 from SDI
14
X
nB
nB
nB
nB
nB
nB
Zwickauer Straße 227
2)
2)
2)
2)
2)
2)
t
w
XX
RDY
Set address register in all channels connected at 0x01:
Write data 0x48 in channel 0x04:
Read L word from register 0x07, one IC existing only:
Configuration of the hardware address in all the channels connected:
Protocol
GEMAC
Gesellschaft für
Mikroe lektronikanwendung Chemnitz mbH
13
0
0
1
1
0
0
1
2 x T
2 x T
1 x T
3 x T
1 x T
4 T
t
t
RDY
Name
Broadcast mode
(Low-active)
Hardware address
Register address
Command
Data word
VDI
OSZ
12
0
1
0
1
0
1
X
OSZ
OSZ
OSZ
OSZ
OSZ
i15
+ 15 ns
+ 15 ns
+ 15 ns
+ 15 ns
+ 15 ns
+ 15 ns
o15
11
X
H3
H3
H3
H3
H3
H3
t
Min
t
VDO
i14
Send bit 14 to SDO
2)
2)
2)
2)
2)
2)
H
10
X
H2
H2
H2
H2
H2
H2
1)
1)
1)
1)
o14
i13
2)
2)
2)
2)
2)
2)
9
X
H1
H1
H1
H1
H1
H1
o13
2)
2)
2)
2)
2)
2)
i12
t
Phone:
Fax::
Internet:
Email:
Date: 20.04.04
t
t
t
SETDI
8
X
H0
H0
H0
H0
H0
H0
L
L
L
o12
4 x T
15 ns
5 T
2)
2)
2)
2)
2)
2)
i11
Description
0:
1:
IP200-Channel address for single access (nB=1)
Default: 0x00
IP200-Register address
Single-word command
Write data
(readed data appears at SDO)
OSZ
7
X
A7
D7
C7
A7
X
X
OSZ
o11
+ 15 ns
i10
+ 15 ns
Command to all channels (for WRA/WRD/WRC only)
Command to the channel addressed by H(3:0)
[phone] - 0
[phone]
www.gemac-chemnitz.de
[e-mail]
[e-mail]
Max
6
X
A6
D6
C6
A6
X
X
o10
i9
5
X
A5
D5
C5
A5
X
X
o9
i8
4
X
A4
D4
C4
A4
X
X
o8
i7
Description
SPI clock, H time
SPI clock, L time
Waiting time between SEN falling and SCLK rising
Switching delay RDY / SDO from SEN
Time between SCLK rising and data read
Setup time SDI before SCLK
Time between SCLK rising and data output
3
X
A3
D3
C3
A3
X
X
Page 12 of 30
o7
i6
2
X
A2
D2
C2
A2
X
X
o6
i5
1
X
A1
D1
C1
A1
X
X
o5
i4
0
X
A0 WRA
D0 WRD
C0 WRC
A0 RD0/ST
X
X
o4
Name
RES
RD1
NOP
Title:
Data Sheet GC-IP200
Name of Document:
43500-DB-2-1-E-IP200.pdf
i3
0x1001
0x6448
0x8007
0x3000
o3
i2
o2
Description
Reserved
Write Address
Write Data
Write Command
Read Byte 0 + 1 (LSB)
Read Byte 2 + 3 (MSB)
Output Read-Register
i1
Start command processing
o1
t
i0
RDY
o0
XX
RDY
1)