IP200 ETC [List of Unclassifed Manufacturers], IP200 Datasheet - Page 22

• Manufacturer Part Number: IP200
• Description: Interpolation Circuit for Incremental Measuring Systems
• Manufacturer: ETC [List of Unclassifed Manufacturers]

9
The IP200 IC does not contain an internal Power-On-Reset circuit! It is essential to supply the IP200
with an external reset signal on pin NRES. This reset signal must appear low until 3ms after VDD rising to a
voltage level of 4.75V.
If NRES and NERR are shorted, the error signal is held through the “NERR -chain” while one of the chain flip-
flops contains a “0”.
9.1
The time between the rising edge of NRES and the rising edge of SDO/RDY, which means the end of the
reset process, amount to approximately 1365 system clocks.
9.2
There are two different types of configuration possible:
Configuration via input pins
Configuration via SPI
Figure 13
D-09116 Chemnitz, Germany
1.
2.
3.
4.
5.
internal NERR
Reset / Configuration
Zwickauer Straße 227
Reset Processing
Configuration
 The register CFG0 will be configured via the input pins IR(2:0), IT(2:1), TRG/GFE and
 All other registers are initialised with default values.
 Suitable for low-cost single-chip and standard applications.
 Pins DP(3:0) select SPI hardware address (for multi-channel systems only).
 Suitable for applications with SPI interface, for example microcontroller systems.
GEMAC
Gesellschaft für
Mikroe lektronikanwendung Chemnitz mbH
Pin SDO/RDY goes to L, all register will be initialised with default values.
The IC is operating a self-calibration, the configuration pins are read into the CFG0 register.
Start of normal operation.
Pin SDO/RDY goes to H (external pull-up required).
The configuration register could be changed via SPI interface.
NRES
SDI/SPEED.
CLK
D
Reset (LOW-active) to
all Flip Flops in the IC
Q
Chain of Flip Flops,
not affected by NRES-Signal
CLK
D
Phone:
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Internet:
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Date: 20.04.04
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IP200
VDD
Page 22 of 30
NRES
NERR
Title:
Data Sheet GC-IP200
Name of Document:
43500-DB-2-1-E-IP200.pdf