IP200 ETC [List of Unclassifed Manufacturers], IP200 Datasheet - Page 14

• Manufacturer Part Number: IP200
• Description: Interpolation Circuit for Incremental Measuring Systems
• Manufacturer: ETC [List of Unclassifed Manufacturers]

5.3
This interface outputs the last activated SPI read register synchronized to the IP200 internal sequential
control counter. The appearing data are separated into two 16-bit words. After reset, the data of the SPI read
register address 0x00(MVAL)appears on DATA(15:0) by default.
Figure 12
To reduce switching noise on the data port the Data outputs DATA(15:8) will be switched 1 clock cycle after
the outputs DATA(7:0). That's why the value at DATA(15:8) is undefined in the clock cycles 0 and 16.
For external components the edges of OUTHIGH can be used to register the new valid data. The level on
OUTHIGH show, which part of the 32-bit read value is active on the data pins (either LSB or MSB). A optional
Strobe-Signal (on pin OREF) can be activated via TSTRB bit in the configuration register TSTCFG.

To get out a desired read register on parallel port, it is necessary to read this register via serial interface first.
EVERY other SPI access at any time can change the behaviour of parallel port.
If the parallel interface be used solely as output port, please select carefully the corresponding attachment
circuit of the configuration and the double function pins at the IP200. Please refer also application notes in
the document 4300x-AN-3-0-E-IPx.pdf.
Sequential
Control Counter
DATA(15:0)
OUTHIGH
STRB
D-09116 Chemnitz, Germany
Signal
T
Zwickauer Straße 227
Parallel Data Port
Delay
GEMAC
XA
Gesellschaft für
Mikroe lektronikanwendung Chemnitz mbH
< 15ns
29
D(31:16)
T
30
Delay
31
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1
D(15:0)
Page 14 of 30
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14
Title:
Data Sheet GC-IP200
Name of Document:
43500-DB-2-1-E-IP200.pdf
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D(31:16)