DSPIC30F MICROCHIP [Microchip Technology], DSPIC30F Datasheet - Page 60

• Manufacturer Part Number: DSPIC30F
• Description: General Purpose and Sensor Families High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

dsPIC30F
• Address Error Trap:
5.
6.
• Stack Error Trap:
• Oscillator Fail Trap:
DS70083G-page 58
This trap is initiated when any of the following
circumstances occurs:
Note:
This trap is initiated under the following
conditions:
This trap is initiated if the external oscillator fails
and operation becomes reliant on an internal RC
backup.
1.
2.
3.
4.
Execution of a “BRA #literal” instruction or a
“GOTO #literal” instruction, where literal
is an unimplemented program memory address.
Executing instructions after modifying the PC to
point to unimplemented program memory
addresses. The PC may be modified by loading
a value into the stack and executing a RETURN
instruction.
1.
2.
A
attempted.
A data fetch from and unimplemented data
memory location is attempted.
A data fetch from an unimplemented pro-
gram memory location is attempted.
An instruction fetch from vector space is
attempted.
The stack pointer is loaded with a value
which is greater than the (user program-
mable) limit value written into the SPLIM
register (stack overflow).
The stack pointer is loaded with a value
which is less than 0x0800 (simple stack
underflow).
In the MAC class of instructions, wherein
the data space is split into X and Y data
space, unimplemented X space includes
all of Y space, and unimplemented Y
space includes all of X space.
misaligned
data
word
access
is
Preliminary
5.3.2
It is possible that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in Figure 5-2 is implemented,
which may require the user to check if other traps are
pending in order to completely correct the fault.
‘Soft’ traps include exceptions of priority level 8 through
level 11, inclusive. The arithmetic error trap (level 11)
falls into this category of traps. Soft traps can be treated
like non-maskable sources of interrupt that adhere to
the priority assigned by their position in the IVT. Soft
traps are processed like interrupts and require 2 cycles
to be sampled and Acknowledged prior to exception
processing. Therefore, additional instructions may be
executed before a soft trap is Acknowledged.
‘Hard’ traps include exceptions of priority level 12
through level 15, inclusive. The address error (level
12), stack error (level 13) and oscillator error (level 14)
traps fall into this category.
Like soft traps, hard traps can also be viewed as non-
maskable sources of interrupt. The difference between
hard traps and soft traps is that hard traps force the
CPU to stop code execution after the instruction caus-
ing the trap has completed. Normal program execution
flow will not resume until after the trap has been
Acknowledged and processed.
If a higher priority trap occurs while any lower priority
trap is in progress, processing of the lower priority trap
will be suspended and the higher priority trap will be
Acknowledged and processed. The lower priority trap
will remain pending until processing of the higher
priority trap completes.
Each hard trap that occurs must be Acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, Acknowledged, or is being processed,
a hard trap conflict will occur. The conflict occurs
because the lower priority trap cannot be Acknowl-
edged until processing for the higher priority trap
completes.
The device is automatically reset in a hard trap conflict
condition. The TRAPR status bit (RCON<15>) is set
when the Reset occurs so that the condition may be
detected in software.
In the case of a math error trap or oscillator failure trap,
the condition that causes the trap to occur must be
removed before the respective trap flag bit in the
INTCON1 register may be cleared.
HARD AND SOFT TRAPS
 2004 Microchip Technology Inc.