DSPIC30F MICROCHIP [Microchip Technology], DSPIC30F Datasheet - Page 66

• Manufacturer Part Number: DSPIC30F
• Description: General Purpose and Sensor Families High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

dsPIC30F
6.4
The dsPIC30F Flash program memory is organized
into rows and panels. Each row consists of 32 instruc-
tions or 96 bytes. Each panel consists of 128 rows or
4K x 24 instructions. RTSP allows the user to erase and
program one row (32 instructions) at a time. RTSP may
be used to program multiple program memory panels,
but the table pointer must be changed at each panel
boundary.
Each panel of program memory contains write latches
that hold 32 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches: instruction 0, instruction 1,
etc. The instruction words loaded must always be from
a group of 32 boundary.
The basic sequence for RTSP programming is to set up
a table pointer, then do a series of TBLWT instructions
to load the write latches. Programming is performed by
setting the special bits in the NVMCON register. Four
TBLWTL and four TBLWTH instructions are required to
load the four instructions. To fully program a row of
program memory, eight cycles of four TBLWTL and four
TBLWTH are required. If multiple panel programming
is required, the table pointer needs to be changed and
the next set of multiple write latches written.
All of the table write operations are single word writes
(2 instruction cycles) because only the table latches are
written. A total of 32 programming passes, each writing
4 instruction words, are required per row.
The Flash program memory is readable, writable, and
erasable during normal operation over the entire V
range.
DS70083G-page 64
RTSP Operation
Preliminary
DD
6.5
The four SFRs used to read and write the program
Flash memory are:
• NVMCON
• NVMADR
• NVMADRU
• NVMKEY
6.5.1
The NVMCON register controls which blocks are to be
erased, which memory type is to be programmed and
start of the programming cycle.
6.5.2
The NVMADR register is used to hold the lower two
bytes of the effective address. The NVMADR register
captures the EA<15:0> of the last table instruction that
has been executed and selects the row to write.
6.5.3
The NVMADRU register is used to hold the upper byte
of the effective address. The NVMADRU register cap-
tures the EA<23:16> of the last table instruction that
has been executed.
6.5.4
NVMKEY is a write only register that is used for write
protection. To start a programming or an erase
sequence, the user must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 6.6 for
further details.
Control Registers
NVMCON REGISTER
NVMADR REGISTER
NVMADRU REGISTER
NVMKEY REGISTER
 2004 Microchip Technology Inc.