ATMEGA169 ATMEL [ATMEL Corporation], ATMEGA169 Datasheet - Page 22

• Manufacturer Part Number: ATMEGA169
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

I/O Memory
General Purpose I/O Registers The ATmega169 contains three General Purpose I/O Registers. These registers can be
General Purpose I/O Register
2 – GPIOR2
General Purpose I/O Register
1 – GPIOR1
General Purpose I/O Register
0 – GPIOR0
22
ATmega169/V
Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD). If the detection
level of the internal BOD does not match the needed detection level, an external low
V
progress, the write operation will be completed provided that the power supply voltage is
sufficient.
The I/O space definition of the ATmega169 is shown in “Register Summary” on page
339.
All ATmega169 I/Os and peripherals are placed in the I/O space. All I/O locations may
be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data
between the 32 general purpose working registers and the I/O space. I/O Registers
within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI
instructions. In these registers, the value of single bits can be checked by using the
SBIS and SBIC instructions. Refer to the instruction set section for more details. When
using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be
used. When addressing I/O Registers as data space using LD and ST instructions, 0x20
must be added to these addresses. The ATmega169 is a complex microcontroller with
more peripheral units than can be supported within the 64 location reserved in Opcode
for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM,
only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike
most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and
can therefore be used on registers containing such Status Flags. The CBI and SBI
instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
used for storing any information, and they are particularly useful for storing global vari-
ables and Status Flags. General Purpose I/O Registers within the address range 0x00 -
0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
CC
reset Protection circuit can be used. If a reset occurs while a write operation is in
MSB
MSB
MSB
R/W
R/W
R/W
7
0
7
0
7
0
R/W
R/W
R/W
6
0
6
0
6
0
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R/W
4
0
4
0
4
0
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
LSB
LSB
LSB
R/W
R/W
R/W
0
0
0
0
0
0
2514P–AVR–07/06
GPIOR2
GPIOR1
GPIOR0