ATMEGA169 ATMEL [ATMEL Corporation], ATMEGA169 Datasheet - Page 29

• Manufacturer Part Number: ATMEGA169
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Clock Output Buffer
Timer/Counter Oscillator
System Clock Prescaler
2514P–AVR–07/06
Table 12. Start-up Times for the External Clock Selection
When applying an external clock, it is required to avoid sudden changes in the applied
clock frequency to ensure stable operation of the MCU. A variation in frequency of more
than 2% from one clock cycle to the next can lead to unpredictable behavior. It is
required to ensure that the MCU is kept in Reset during such changes in the clock
frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of
the internal clock frequency while still ensuring stable operation. Refer to “System Clock
Prescaler” on page 29 for details.
When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This
mode is suitable when chip clock is used to drive other circuits on the system. The clock
will be output also during reset and the normal operation of I/O pin will be overridden
when the fuse is programmed. Any clock source, including internal RC Oscillator, can be
selected when CLKO serves as clock output. If the System Clock Prescaler is used, it is
the divided system clock that is output when the CKOUT Fuse is programmed.
ATmega169 share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1
and XTAL2. This means that the Timer/Counter Oscillator can only be used when the
calibrated internal RC Oscillator is selected as system clock source. The Oscillator is
optimized for use with a 32.768 kHz watch crystal. See Figure 12 on page 25 for crystal
connection.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Reg-
ister is written to logic one. See “Asynchronous operation of the Timer/Counter” on page
138 for further description on selecting external clock as input instead of a 32 kHz
crystal.
The ATmega169 system clock can be divided by setting the “Clock Prescale Register –
CLKPR” on page 30. This feature can be used to decrease the system clock frequency
and power consumption when the requirement for processing power is low. This can be
used with all clock source options, and it will affect the clock frequency of the CPU and
all synchronous peripherals. clk
shown in Table 13.
When switching between prescaler settings, the System Clock Prescaler ensures that
no glitches occur in the clock system and that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock fre-
quency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided
clock, which may be faster than the CPU’s clock frequency. Hence, it is not possible to
determine the state of the prescaler – even if it were readable, and the exact time it
takes to switch from one clock division to another cannot be exactly predicted. From the
SUT1..0
00
01
10
11
Start-up Time from Power-
down and Power-save
6 CK
6 CK
6 CK
I/O
, clk
ADC
, clk
Additional Delay from
Reset (V
Reserved
14CK + 4.1 ms
CPU
14CK + 65 ms
, and clk
14CK
CC
= 5.0V)
FLASH
ATmega169/V
are divided by a factor as
Recommended Usage
BOD enabled
Fast rising power
Slowly rising power
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