AT90PWM2B-16SE ATMEL [ATMEL Corporation], AT90PWM2B-16SE Datasheet - Page 85
AT90PWM2B-16SE
Manufacturer Part Number
AT90PWM2B-16SE
Description
8-bit Microcontroller with 8K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT90PWM2B-16SE.pdf
(361 pages)
- Current page: 85 of 361
- Download datasheet (7Mb)
14. 8-bit Timer/Counter0 with PWM
14.1
14.1.1
4317J–AVR–08/10
Overview
Definitions
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output
Compare Units, and with PWM support. It allows accurate program execution timing (event man-
agement) and wave generation. The main features are:
•
•
•
•
•
•
•
A simplified block diagram of the 8-bit Timer/Counter is shown in
placement of I/O pins, refer to
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-
tions are listed in the
The PRTIM0 bit in
Timer/Counter0 module.
Figure 14-1. 8-bit Timer/Counter Block Diagram
Many register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-
pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or
bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing
Timer/Counter0 counter value and so on.
Two Independent Output Compare Units
Double Buffered Output Compare Registers
Clear Timer on Compare Match (Auto Reload)
Glitch Free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
Timer/Counter
OCRnx
TCCRnA
OCRnx
TCNTn
=
=
“Power Reduction Register” on page 42
“8-bit Timer/Counter Register Description” on page
direction
count
clear
“Pin Descriptions” on page
TOP
=
TCCRnB
Control Logic
Values
BOTTOM
Fixed
TOP
=
0
clk
Tn
Generation
Waveform
Generation
Waveform
AT90PWM2/3/2B/3B
Clock Select
( From Prescaler )
Detector
Edge
8. CPU accessible I/O Registers,
must be written to zero to enable
Figure
95.
OCnB
(Int.Req.)
14-1. For the actual
OCnB
OCnA
(Int.Req.)
OCnA
TOVn
(Int.Req.)
Tn
85
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