P89LV51RD2BA PHILIPS [NXP Semiconductors], P89LV51RD2BA Datasheet - Page 17

• Manufacturer Part Number: P89LV51RD2BA
• Description: 8-bit 80C51 3 V low power 64 kB Flash microcontroller with 1 kB RAM
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9397 750 14101
Product data
Since the upper 128 bytes occupy the same addresses as the SFRs, the RAM must
be accessed indirectly. The RAM and SFRs space are physically separate even
though they have the same addresses.
Table 7:
Not bit addressable; Reset value 00H
Table 8:
When instructions access addresses in the upper 128 bytes (above 7FH), the MCU
determines whether to access the SFRs or RAM by the type of instruction given. If it
is indirect, then RAM is accessed. If it is direct, then an SFR is accessed. See the
examples below.
Indirect Access:
Register R0 points to 90H which is located in the upper address range. Data in
‘#data’ is written to RAM location 90H rather than port 1.
Direct Access:
Data in ‘#data’ is written to port 1. Instructions that write directly to the address write
to the SFRs.
To access the expanded RAM, the EXTRAM bit must be cleared and MOVX
instructions must be used. The extra 768 bytes of memory is physically located on the
chip and logically occupies the first 768 bytes of external memory (addresses 000H to
2FFH).
Bit
7 to 2
1
0
Bit
Symbol
4. The expanded RAM of 768 bytes (00H to 2FFH) is indirectly addressable by the
MOV@R0, #data; R0 contains 90H
MOV90H, #data; write data to P1
move external instruction (MOVX) and clearing the EXTRAM bit. (See ‘Auxiliary
Register (AUXR) in
AUXR - Auxiliary register (address 8EH) bit allocation
AUXR - Auxiliary register (address 8EH) bit description
Symbol
-
EXTRAM
AO
7
-
Rev. 03 — 11 October 2004
6
-
Section 6 “Special function registers” on page
Description
Reserved for future use. Should be set to ‘0’ by user programs.
Internal/External RAM access using MOVX @Ri/@DPTR.
When ‘0’, core attempts to access internal XRAM with address
specified in MOVX instruction. If address supplied with this
instruction exceeds on-chip available XRAM, off-chip XRAM is
going to be selected and accessed.
When ‘1’, every MOVX @Ri/@DPTR instruction targets external
data memory by default.
ALE off: disables/enables ALE. AO = 0 results in ALE emitted at a
constant rate of
is active only during a MOVX or MOVC.
5
-
1
2
4
the oscillator frequency. In case of AO = 1, ALE
-
8-bit microcontrollers with 80C51 core
3
-
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P89LV51RD2
2
-
EXTRAM
1
10)
17 of 77
AO
0