P89LV51RD2BA PHILIPS [NXP Semiconductors], P89LV51RD2BA Datasheet - Page 42

• Manufacturer Part Number: P89LV51RD2BA
• Description: 8-bit 80C51 3 V low power 64 kB Flash microcontroller with 1 kB RAM
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9397 750 14101
Product data
7.6.1 SPI features
7.6.2 SPI description
7.6 Serial peripheral interface
Table 29:
In the above example the differentiation among the 3 slaves is in the lower 3 address
bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110.
Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 0101. Slave
2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and
1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1
to exclude slave 2. The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are treated as don’t-cares. In
most cases, interpreting the don’t-cares as ones, the broadcast address will be FF
hexadecimal. Upon reset SADDR and SADEN are loaded with 0s. This produces a
given address of all ‘don’t cares’ as well as a Broadcast address of all ‘don’t cares'.
This effectively disables the Automatic Addressing mode and allows the
microcontroller to use standard UART drivers which do not make use of this feature.
The serial peripheral interface (SPI) allows high-speed synchronous data transfer
between the P89LV51RD2 and peripheral devices or between several P89LV51RD2
devices.
devices. The SCK pin is the clock output and input for the master and slave modes,
respectively. The SPI clock generator will start following a write to the master devices
SPI data register. The written data is then shifted out of the MOSI pin on the master
device into the MOSI pin of the slave device. Following a complete transmission of
one byte of data, the SPI clock generator is stopped and the SPIF flag is set. An SPI
interrupt request will be generated if the SPI Interrupt Enable bit (SPIE) and the Serial
Port Interrupt Enable bit (ES) are both set.
Slave 0
Slave 1
Slave 2
•
•
•
•
•
•
•
Master or slave operation
10 MHz bit frequency (max)
LSB first or MSB first data transfer
Four programmable bit rates
End of transmission (SPIF)
Write collision flag protection (WCOL)
Wake-up from idle mode (slave mode only)
Figure 17
SADDR = 1110 0000
SADEN = 1111 1001
Given =
SADDR = 1110 0000
SADEN = 1111 1010
Given =
SADDR = 1110 0000
SADEN = 1111 1100
Given =
Slaves 0, 1 and 2 scheme examples
Rev. 03 — 11 October 2004
shows the correspondence between master and slave SPI
1110 0XX0
1110 0X0X
1110 00XX
8-bit microcontrollers with 80C51 core
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P89LV51RD2
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