P87C660X2 PHILIPS [NXP Semiconductors], P87C660X2 Datasheet - Page 32

• Manufacturer Part Number: P87C660X2
• Description: 80C51 8-bit microcontroller family
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
2. Master Receiver Mode:
3. Slave Receiver Mode:
2003 Oct 02
SDA
SCL
80C51 8-bit microcontroller family
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I
of the receiving device (7 bytes) and the data direction bit. In this
case the data direction bit (R/W) will be logic 0, and we say that
a “W” is transmitted. Thus the first byte transmitted is SLA+W.
Serial data is transmitted 8 bits at a time. After each byte is
transmitted, an acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the end of a
serial transfer.
The first byte transmitted contains the slave address of
the transmitting device (7 bits) and the data direction bit. In this
case, the data direction bit (R/W) will be logic 1, and we say that
an “R” is transmitted. Thus the first byte transmitted is SLA+R.
Serial data is received via P1.7/SDA while P1.6/SCL outputs the
serial clock. Serial data is received 8 bits at a time. After each
byte is received an acknowledge bit is transmitted. START and
STOP conditions are output to indicate the beginning and end of
a serial transfer.
Serial data and the serial clock are received through P1.7/SDA
and P1.6/SCL. After each byte is received, an acknowledge bit is
CONDITION
START
S
I
2
C bus
MSB
1
2
C interfaces
SLAVE ADDRESS
2
P1.7/SDA
P8xC66xX2
P1.6/SCL
7
16 KB OTP/ROM, 512B
Figure 15. Typical I
DIRECTION
Figure 16. Data Transfer on the I
SIGNAL FROM RECEIVER
ACKNOWLEDGMENT
R/W
BIT
8
OTHER DEVICE WITH
ACK
9
I
R
2
P
C INTERFACE
32
2
C Bus Configuration
4. Slave Transmitter Mode:
In a given application, SIO1 may operate as a master and as a
slave. In the slave mode, the SIO1 hardware looks for its own slave
address and the general call address. If one of these addresses is
detected, an interrupt is requested. When the microcontroller wishes
to become the bus master, the hardware waits until the bus is free
before the master mode is entered so that a possible slave action is
not interrupted. If bus arbitration is lost in the master mode, SIO1
switches to the slave mode immediately and can detect its own
slave address in the same serial transfer.
R
P
transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is
performed by hardware after reception of the slave address and
direction bit.
The first byte is received and handled as in the slave receiver
mode. However, in this mode, the direction bit will indicate that
the transfer direction is reversed. Serial data is transmitted via
P1.7/SDA while the serial clock is input through P1.6/SCL.
START and STOP conditions are recognized as the beginning
and end of a serial transfer.
V
1
CLOCK LINE HELD LOW WHILE
INTERRUPTS ARE SERVICED
DD
REPEATED IF MORE BYTES
ARE TRANSFERRED
2
C Bus
2
OTHER DEVICE WITH
SIGNAL FROM RECEIVER
I
2
3–8
C INTERFACE
ACKNOWLEDGMENT
P8xC660X2/661X2
ACK
9
SU01748
SDA
SCL
P/S
Product data
CONDITION
CONDITION
REPEATED
SU00965
START
STOP