LPC2919 PHILIPS [NXP Semiconductors], LPC2919 Datasheet - Page 46

• Manufacturer Part Number: LPC2919
• Description: ARM9 microcontroller with CAN and LIN
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
LPC2917_19_1
Preliminary data sheet
8.8.4.4 CGU pin description
Triple output phases
For applications that require multiple clock phases two additional clock outputs can be
enabled by setting register P23EN to ’1’, thus giving three clocks with a 120° phase
difference. In this mode all three clocks generated by the analog section are sent to the
output dividers. When the PLL has not yet achieved lock the second and third phase
output dividers run unsynchronized, which means that the phase relation of the output
clocks is unknown. When the PLL LOCK register is set the second and third phase of the
output dividers are synchronized to the main output clock CLKOUT PLL, thus giving three
clocks with a 120° phase difference.
Direct output mode
In normal operating mode (with DIRECT set to ’0’) the CCO clock is divided by 2, 4, 8 or
16 depending on the value on the PSEL[1:0] input, giving an output clock with a 50% duty
cycle. If a higher output frequency is needed the CCO clock can be sent directly to the
output by setting DIRECT to ’1’. Since the CCO does not directly generate a 50% duty
cycle clock, the output clock duty cycle in this mode can deviate from 50%.
Power-down control
A power-down mode has been incorporated to reduce power consumption when the PLL
clock is not needed. This is enabled by setting the PD control register bit. In this mode the
analog section of the PLL is turned off, the oscillator and the phase-frequency detector are
stopped and the dividers enter a reset state. While in power-down mode the LOCK output
is low, indicating that the PLL is not in lock. When power-down mode is terminated by
clearing the PD control-register bit the PLL resumes normal operation, and makes the
LOCK signal high once it has regained lock on the input clock.
The CGU module in the LPC2917/19 has the pins listed in
Table 24.
Symbol
XOUT_OSC
XIN_OSC
Fig 14. PLL block diagram
Input clock
CGU pins
in
Direction
out
CCO
Rev. 1.01 — 15 November 2007
Description
Oscillator crystal output
Oscillator crystal input or external clock input
Bypass
/ MDIV
/ 2PDIV
ARM9 microcontroller with CAN and LIN
MSEL
PSEL
Direct
Table 24
LPC2917/19
P23
P23EN
below.
© NXP B.V. 2007. All rights reserved.
clkout120 /
clkout240
clkout
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