MC9S12A128 MOTOROLA [Motorola, Inc], MC9S12A128 Datasheet - Page 26
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MC9S12A128
Manufacturer Part Number
MC9S12A128
Description
Microcontroller unit (MCU)
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC9S12A128.pdf
(92 pages)
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MC9S12A128 Device Guide — V01.01
2.2 Signal Properties Summary
Table 2-1
package.
Function 1
Pin Name
PAD[06:00]
PAD[14:8]
VREGEN
RESET
PA[7:0]
PB[7:0]
EXTAL
PAD15
PAD07
26
BKGD
TEST
XTAL
XFC
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
summarizes the pin functionality. Signals shown in bold are not available in the 80 pin
Function 2
ADDR[15:8]/
Pin Name
DATA[15:8]
ADDR[7:0]/
AN[14:08]
AN[06:00]
DATA[7:0]
NOACC
LSTRB
TAGHI
IPIPE1
IPIPE0
KWH7
KWH6
KWH5
KWH4
KWH3
KWH2
KWH1
KWH0
ECLK
AN15
AN07
XIRQ
R/W
IRQ
—
—
—
—
—
—
Function 3
Pin Name
ETRIG1
ETRIG0
TAGLO
XCLKS
MODC
MOSI1
MISO1
MODB
MODA
SCK1
SS1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 2-1 Signal Properties
Function 4
Pin Name
—
—
—
—
—
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DDPLL
N.A.
DDPLL
DDR
DDR
DDR
DDX
DDA
Oscillator Pins
External Reset
Test Input
Voltage Regulator Enable Input
PLL Loop Filter
Background Debug, Tag High, Mode Input
Port AD Input, Analog Input AN7 of
ATD1, External Trigger Input of ATD1
Port AD Inputs, Analog Inputs AN[6:0]
of ATD1
Port AD Input, Analog Input AN7 of ATD0,
External Trigger Input of ATD0
Port AD Inputs, Analog Inputs AN[6:0] of
ATD0
Port A I/O, Multiplexed Address/Data
Port B I/O, Multiplexed Address/Data
Port E I/O, Access, Clock Select
Port E I/O, Pipe Status, Mode Input
Port E I/O, Pipe Status, Mode Input
Port E I/O, Bus Clock Output
Port E I/O, Byte Strobe, Tag Low
Port E I/O, R/W in expanded modes
Port E Input, Maskable Interrupt
Port E Input, Non Maskable Interrupt
Port H I/O, Interrupt
Port H I/O, Interrupt
Port H I/O, Interrupt
Port H I/O, Interrupt
Port H I/O, Interrupt, SS of SPI1
Port H I/O, Interrupt, SCK of SPI1
Port H I/O, Interrupt, MOSI of SPI1
Port H I/O, Interrupt, MISO of SPI1
Description