MC9S12A128 MOTOROLA [Motorola, Inc], MC9S12A128 Datasheet - Page 75
![no-image](/images/no-image-200.jpg)
MC9S12A128
Manufacturer Part Number
MC9S12A128
Description
Microcontroller unit (MCU)
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC9S12A128.pdf
(92 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12A128BCFU
Manufacturer:
SIEMENS
Quantity:
3 274
Company:
Part Number:
MC9S12A128BCFU
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12A128BCFU
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MC9S12A128BCFUE
Manufacturer:
EEMB
Quantity:
100
Company:
Part Number:
MC9S12A128BCPV
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC9S12A128CFUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12A128CFUE
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MC9S12A128CPV
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MC9S12A128CPVE
Manufacturer:
FREESCALE
Quantity:
2 390
Part Number:
MC9S12A128CPVE
Manufacturer:
FREESCALE
Quantity:
20 000
A.5.1.4 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
A.5.1.5 Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After t
fetching the interrupt vector.
A.5.2 Oscillator
The device features an internal Colpitts oscillator. By asserting the XCLKS input during reset this
oscillator can be bypassed allowing the input of a square wave. Before asserting the oscillator to the
internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP
or oscillator fail. t
POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum
oscillator start-up time t
asserted if the frequency of the incoming clock signal is below the Assert Frequency f
Conditions are shown in
Num C
NOTES:
1. f
2. Maximum value is for extreme cases using high Q, low frequency crystals
3. XCLKS =0 during reset
10
11
12
13
1
2
3
4
5
6
7
8
9
osc
C Crystal oscillator range
P Startup Current
D Oscillator start-up time from POR or STOP
C Oscillator start-up time
D Clock Quality check time-out
P Clock Monitor Failure Assert Frequency
P External square wave input frequency
D External square wave pulse width low
D External square wave pulse width high
D External square wave rise time
D External square wave fall time
D Input Capacitance (EXTAL, XTAL pins)
C
= 4MHz, C = 22pF.
DC Operating Bias in Colpitts Configuration on
EXTAL Pin
CQOUT
Table A-4
UPOSC
specifies the maximum time before switching to the internal self clock mode after
Rating
unless otherwise noted
. The device also features a clock monitor. A Clock Monitor Failure is
Table A-15 Oscillator Characteristics
(3)
Symbol
V
n
t
t
UPOSC
CQOUT
f
t
t
UPOSC
t
t
DCBIAS
f
I
CMFA
f
EXTL
EXTH
EXTR
EXTF
OSC
OSC
C
EXT
IN
4100
Min
0.45
100
MC9S12A128 Device Guide — V01.01
0.5
0.5
9.5
9.5
50
—
—
—
—
—
Typ
100
8
1.1
—
—
—
—
—
—
—
—
9
(1)
wrs
CMFA.
the CPU starts
100
Max
200
2.5
16
50
—
—
—
—
—
—
1
1
(2)
cyc
Unit
MHz
MHz
KHz
ms
pF
ns
ns
ns
ns
V
s
OSC
A
75