MC9S12A128 MOTOROLA [Motorola, Inc], MC9S12A128 Datasheet - Page 74

• Manufacturer Part Number: MC9S12A128
• Description: Microcontroller unit (MCU)
• Manufacturer: MOTOROLA [Motorola, Inc]

A.5 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-14
the startup behavior can be found in the HCS12 Clock and Reset Generator (CRG) Block Guide (Motorola
document order number, S12CRGV3/D) .
A.5.1.1 POR
The release level V
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t
clock. The fastest startup time possible is given by n
A.5.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when V
the PORF bit in the CRG Flags Register has not been set.
A.5.1.3 External Reset
When external reset is asserted for a time greater than PW
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
Conditions are shown in
Num C
1
2
3
4
5
6
D Reset input pulse width, minimum input time
D Startup from Reset
D Interrupt pulse width, IRQ edge-sensitive mode
D Wait recovery startup time
T POR release level
T POR assert level
DD5
summarizes several startup characteristics explained in this section. Detailed description of
is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
PORR
Table A-4
and the assert level V
CQOUT
Rating
unless otherwise noted
Table A-14 Startup Characteristics
no valid oscillation is detected, the MCU will start using the internal self
PORA
are derived from the V
uposc
Symbol
PW
V
PW
V
n
t
.
PORR
PORA
WRS
RST
RSTL
RSTL
IRQ
the CRG module generates an internal
Min
0.97
192
MC9S12A128 Device Guide — V01.01
20
—
—
2
DD
supply. They are also valid
Typ
—
—
—
—
—
—
Max
2.07
196
14
—
—
—
Unit
n
t
t
osc
ns
cyc
V
V
osc
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