TMS470R1B512 AD [Analog Devices], TMS470R1B512 Datasheet - Page 10

• Manufacturer Part Number: TMS470R1B512
• Description: 16/32-Bit RISC Flash Microcontroller
• Manufacturer: AD [Analog Devices]

TMS470R1B512
16/32-Bit RISC Flash Microcontroller
SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006
10
CLKOUT
PORRST
RST
AWD
TCK
TDI
TDO
TEST
TMS
TMS2
TRST
FLTP1
FLTP2
V
V
CCP
CC
NAME
TERMINAL
NO.
120
121
134
133
135
128
132
83
32
15
72
76
74
75
38
37
14
31
55
86
93
3.3-V PWR
1.8-V PWR
TYPE
3.3-V I/O
3.3-V I/O
3.3-V I/O
3.3-V O
3.3-V I
3.3-V I
3.3-V I
3.3-V I
3.3-V I
3.3-V I
3.3-V I
NC
NC
(1) (2)
Table 2. Terminal Functions (continued)
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
PULLDOWN
IPD (20 A)
IPD (20 A)
IPU (20 A)
IPD (20 A)
IPD (20 A)
IPU (20 A)
IPD (20 A)
IPD (20 A)
IPU (20 A)
IPU (20 A)
IPD (20 A)
INTERNAL
PULLUP/
SUPPLY VOLTAGE CORE (1.8 V)
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SYSTEM MODULE (SYS)
(3)
TEST/DEBUG (T/D)
Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output
of SYSCLK, ICLK, or MCLK.
Input master chip power-up reset. External V
assert a power-on reset.
Bidirectional reset. The internal circuitry can assert a reset, and an external
system reset can assert a device reset.
On this pin, the output buffer is implemented as an open drain (drives low
only).
To ensure an external reset is not arbitrarily generated, TI recommends
that an external pullup resistor be connected to this pin.
Analog watchdog reset. The AWD pin provides a system reset if the WD
KEY is not written in time by the system, providing an external RC network
circuit is connected.
If the user is not using AWD, TI recommends that this pin be connected to
ground or pulled down to ground by an external resistor.
For more details on the external RC network circuit, see the TMS470R1x
System Module Reference Guide (literature number SPNU189).
Test clock. TCK controls the test hardware (JTAG).
Test data in. TDI inputs serial data to the test instruction register, test data
register, and programmable test address (JTAG).
Test data out. TDO outputs serial data from the test instruction register,
test data register, identification register, and programmable test address
(JTAG).
Test enable. Reserved for internal use only. TI recommends that this pin
be connected to ground or pulled down to ground by an external resistor.
Serial input for controlling the state of the CPU test access port (TAP)
controller (JTAG)
Serial input for controlling the second TAP. TI recommends that this pin be
connected to VCCIO or pulled up to VCCIO by an external resistor.
Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG)
Boundary-Scan Logic. TI recommends that this pin be pulled down to
ground by an external resistor.
Flash test pad 1. For proper operation, this pin must not be connected
[no connect (NC)].
Flash test pad 2. For proper operation, this pin must not be connected
[no connect (NC)].
Flash external pump voltage (3.3 V). This pin is required for both flash
read and flash program and erase operations.
Core logic supply voltage
FLASH
DESCRIPTION
CC
monitor circuitry must
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