TMS470R1B512 AD [Analog Devices], TMS470R1B512 Datasheet - Page 34

• Manufacturer Part Number: TMS470R1B512
• Description: 16/32-Bit RISC Flash Microcontroller
• Manufacturer: AD [Analog Devices]

TMS470R1B512
16/32-Bit RISC Flash Microcontroller
SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006
34
SPIn MASTER MODE TIMING PARAMETERS
SPIn Master Mode External Timing Parameters
(CLOCK PHASE = 0, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input)
(1) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
(2) t
(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(4) When the SPI is in master mode, the following must be true:
(5) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
NO.
2
3
4
5
6
7
1
(5)
(5)
(5)
(5)
(5)
(5)
For PS values from 1 to 255: t
For PS values of 0: t
c(ICLK)
t
t
t
t
t
t
t
t
t
t
t
t
t
c(SPC)M
w(SPCH)M
w(SPCL)M
w(SPCL)M
w(SPCH)M
d(SPCH-SIMO)M
d(SPCL-SIMO)M
v(SPCL-SIMO)M
v(SPCH-SIMO)M
su(SOMI-SPCL)M
su(SOMI-SPCH)M
v(SPCL-SOMI)M
v(SPCH-SOMI)M
(clock polarity = 0)
(clock polarity = 1)
= interface clock cycle time = 1/f
SPInSIMO
SPInSOMI
SPInCLK
SPInCLK
Cycle time, SPInCLK
Pulse duration, SPInCLK high (clock polarity = 0)
Pulse duration, SPInCLK low (clock polarity = 1)
Pulse duration, SPInCLK low (clock polarity = 0)
Pulse duration, SPInCLK high (clock polarity = 1)
Delay time, SPInCLK high to SPInSIMO valid (clock polarity = 0)
Delay time, SPInCLK low to SPInSIMO valid (clock polarity = 1)
Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0)
Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1)
Setup time, SPInSOMI before SPInCLK low (clock polarity = 0)
Setup time, SPInSOMI before SPInCLK high (clock polarity = 1)
Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 0)
Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 1)
c(SPC)M
Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 0)
= 2t
c(SPC)M
c(ICLK)
(ICLK)
(PS +1)t
100 ns.
(4)
c(ICLK)
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2
4
Master Out Data Is Valid
100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
Master In Data
Must Be Valid
6
1
5
3
7
(1) (2) (3)
t
t
0.5t
0.5t
0.5t
0.5t
c(SPC)M
c(SPC)M
(see
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
MIN
100
6
6
4
4
– 5 – t
– 5 – t
Figure
– t
– t
– t
– t
r
f
f
r
f
r
12)
0.5t
0.5t
0.5t
0.5t
256t
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
MAX
10
10
c(ICLK)
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+ 5
+ 5
+ 5
+ 5
UNIT
ns
ns
ns
ns
ns
ns
ns