TMS470R1B512 AD [Analog Devices], TMS470R1B512 Datasheet - Page 40

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TMS470R1B512

Manufacturer Part Number
TMS470R1B512
Description
16/32-Bit RISC Flash Microcontroller
Manufacturer
AD [Analog Devices]
Datasheet

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TMS470R1B512
16/32-Bit RISC Flash Microcontroller
SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006
40
SCIn ISOSYNCHRONOUS MODE TIMINGS EXTERNAL CLOCK
Timing Requirements for External Clock SCIn Isosynchronous Mode
(see
(1) t
(2) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(3) When driving an external SCInCLK, the following must be true: t
t
t
t
t
t
t
t
c(SCC)
w(SCCH)
w(SCCL)
d(SCCH-TXV)
v(TX)
su(RX-SCCL)
v(SCCL-RX)
c(ICLK)
Figure
A.
Data transmission / reception characteristics for isosynchronous mode with external clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the
SCICLK falling edge.
= interface clock cycle time = 1/f
17)
SCICLK
Cycle time, SCInCLK
Pulse duration, SCInCLK high
Pulse duration, SCInCLK low
Delay time, SCInCLK high to SCInTX valid
Valid time, SCInTX data after SCInCLK low
Setup time, SCInRX before SCInCLK low
Valid time, SCInRX data after SCInCLK low
SCIRX
SCITX
Figure 17. SCIn Isosynchronous Mode Timing Diagram for External Clock
(3)
(ICLK)
t
w(SCCL)
t
d(SCCH TXV)
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t
c(SCC)
c(SCC)
t
w(SCCH)
t
su(RX SCCL)
8t
c(ICLK)
0.5t
0.5t
Data Valid
c(SCC)
c(SCC)
.
2t
2t
Data Valid
c(ICLK)
c(SCC)
8t
t
v(TX)
MIN
c(ICLK)
– 0.25t
– 0.25t
0
– 10
+ 10
c(ICLK)
c(ICLK)
(1) (2)
0.5t
0.5t
t
v(SCCL RX)
2t
c(SCC)
c(SCC)
c(ICLK)
MAX
+ 0.25t
+ 0.25t
+ 12 + t
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c(ICLK)
c(ICLK)
r
UNIT
ns
ns
ns
ns
ns
ns
ns

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