TMS470R1B512 AD [Analog Devices], TMS470R1B512 Datasheet - Page 28

• Manufacturer Part Number: TMS470R1B512
• Description: 16/32-Bit RISC Flash Microcontroller
• Manufacturer: AD [Analog Devices]

TMS470R1B512
16/32-Bit RISC Flash Microcontroller
SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006
28
ZPLL AND CLOCK SPECIFICATIONS
Timing Requirements for ZPLL Circuits Enabled or Disabled
(1) Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1)
Switching Characteristics Over Recommended Operating Conditions for Clocks
(1) When PLLDIS = 0, f
(2) f
(3) Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
(4) Flash Vread must be set to 5 V to achieve maximum system clock frequency.
f
t
t
t
f
f
f
f
f
t
t
t
t
(OSC)
c(OSC)
w(OSCIL)
w(OSCIH)
(OSCRST)
(SYS)
(CONFIG)
(ICLK)
(ECLK)
c(SYS)
c(CONFIG)
c(ICLK)
c(ECLK)
bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
CLKDIVPRE [2:0] bits in the global control register (GLBCTRL[2:0]) and M is the PLL multiplier determined by the MULT4 bit
(GLBCTRL.3).
When PLLDIS = 1, f
f
bits in the SYS module.
(ECLK)
(ICLK)
= f
= f
(SYS)
(ICLK)
Input clock frequency
Cycle time, OSCIN
Pulse duration, OSCIN low
Pulse duration, OSCIN high
OSC FAIL frequency
System clock frequency
System clock frequency
Interface clock frequency
External clock output frequency for ECP module
Cycle time, system clock
Cycle time, system clock
Cycle time, interface clock
Cycle time, ECP module external clock output
/X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1]
/N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
(SYS)
(SYS)
= M × f
= f
PARAMETER
(OSC)
(1)
(OSC)
/R, where R = {1,2,3,4,5,6,7,8}.
(4)
/R, where M = {4 or 8}, R = {1,2,3,4,5,6,7,8}. R is the system-clock divider determined by the
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Pipeline mode enabled
Pipeline mode disabled
Flash config mode
Pipeline mode enabled
Pipeline mode disabled
Pipeline mode enabled
Pipeline mode disabled
Flash config mode
Pipeline mode enabled
Pipeline mode disabled
TEST CONDITIONS
(3)
16.7
41.6
41.6
41.6
MIN
MIN
40
40
50
15
15
(1) (2)
4
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MAX
MAX
60
24
24
25
25
24
20
53
UNIT
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns