HT83F10 HOLTEK [Holtek Semiconductor Inc], HT83F10 Datasheet - Page 34

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HT83F10

Manufacturer Part Number
HT83F10
Description
Flash Type Voice OTP MCU
Manufacturer
HOLTEK [Holtek Semiconductor Inc]
Datasheet
Interrupt Priority
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In case of simultaneous requests, the
accompanying table shows the priority that is applied.
Suitable masking of the individual interrupts using the
INTC and INTCH registers can prevent simultaneous
occurrences.
Rev. 1.00
Time Base Interrupt
Timer 0 Overflow
Timer 1 Overflow
SIM Interrupt
Interrupt Source
Interrupt
Vector
0CH
04H
08H
14H
HT83FXX
Priority
1
2
3
4
Interrupt Structure
INTCH Register
34
Time Base Interrupt
Each device contains a Time Base whose correspond-
ing interrupt enable bits are known as ETBI and is lo-
cated in the INTC register. For a Time Base generated
interrupt to occur, the corresponding Time Base inter-
rupt enable bit must be first set. Time Base also has a
corresponding Time Base interrupt request flag, which
is known as TBF, also located in the INTC register.
When the master interrupt and corresponding timer in-
terrupt enable bits are enabled, the stack is not full, and
when the corresponding timer overflows a subroutine
call to the corresponding Time Base interrupt vector will
occur. The corresponding Program Memory vector loca-
tions for the Time Base is 04H. After entering the inter-
rupt execution routine, the corresponding interrupt
request flag, TBF will be reset and the EMI bit will be
cleared to disable other interrupts.
HT83FXX
May 12, 2009

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