HT83F10 HOLTEK [Holtek Semiconductor Inc], HT83F10 Datasheet - Page 35

• Manufacturer Part Number: HT83F10
• Description: Flash Type Voice OTP MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Timer Interrupt
For a timer generated interrupt to occur, the correspond-
ing timer interrupt enable bit must be first set. Each de-
vice contains two 8-bit timers whose corresponding
interrupt enable bits are known as ET0 and ET1and are
located in the INTC register. Each timer also has a cor-
responding timer interrupt request flag, which are
known as T0F and T1F, also located in the INTC regis-
ter. When the master interrupt and corresponding timer
interrupt enable bits are enabled, the stack is not full,
and when the corresponding timer overflows a subrou-
tine call to the corresponding timer interrupt vector will
occur. The corresponding Program Memory vector loca-
tions for Timer 0 and Timer1 are 08H and 0CH. After en-
tering the interrupt execution routine, the corresponding
interrupt request flags, T0F or T1F will be reset and the
EMI bit will be cleared to disable other interrupts.
Serial Interface Module - SIM - Interrupt
SIM Interrupts include both the SPI and I
The SIM Mode is determined by the SIM2, SIM1 and
SIM0 bits in the SIMC0 register.
For a SPI Interrupt to occur, the global interrupt enable
bit, EMI, and the corresponding SIM interrupt enable bit,
ESII, must be first set. The SIMEN bit in the SIMC0 reg-
ister must also be set. An actual SPI Interrupt will take
place when the flag, SIF, is set, a situation that will occur
when 8-bits of data are transferred or received from ei-
ther of the SPI interfaces. When the interrupt is enabled,
the stack is not full and an SIM interrupt occurs, a sub-
routine call to the SIM interrupt vector at location 14H,
will take place. When the interrupt is serviced, the SPI
interrupt request flag, SIF, will be automatically reset
and the EMI bit will be automatically cleared to disable
other interrupts.
Rev. 1.00
2
C Interrupts.
35
For an I
enable bit ESII must be first set. An actual I
will be initialized when the SIM interrupt request flag,
SIF, is set, a situation that will occur when a matching
I
an I
the stack is not full and a SIM interrupt occurs, a subrou-
tine call to the SIM interrupt vector at location 14H, will
take place When an I
quest flag SIF will be reset and the EMI bit will be
cleared to disable other interrupts.
Programming Considerations
By disabling the interrupt enable bits, a requested inter-
rupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the INTC or INTCH register until the corre-
sponding interrupt is serviced or until the request flag is
cleared by a software instruction.
It is recommended that programs do not use the CALL
subroutine instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well con-
trolled, the original control sequence will be damaged
once a CALL subroutine is executed in the interrupt
subroutine.
All of these interrupts have the capability of waking up
the processor when in the Power Down Mode. Only the
Program Counter is pushed onto the stack. If the con-
tents of the register or status register are altered by the
interrupt service program, which may corrupt the de-
sired control sequence, then the contents should be
saved in advance.
2
C slave address is received or from the completion of
2
C data byte transfer. When the interrupt is enabled,
2
C interrupt to occur, the corresponding interrupt
2
C interrupt occurs, the interrupt re-
HT83FXX
May 12, 2009
2
C interrupt