ATA5771_09 ATMEL [ATMEL Corporation], ATA5771_09 Datasheet - Page 134
ATA5771_09
Manufacturer Part Number
ATA5771_09
Description
Microcontroller with UHF ASK/FSK Transmitter
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATA5771_09.pdf
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13.7.4
7701C–AVR–12/08
Phase Correct PWM Mode
ture is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output
Compare unit is enabled in the fast PWM mode.
The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-slope
operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-
TOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In non-
inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match
between TCNT0 and OCR0x while upcounting, and set on the Compare Match while down-
counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation
has lower maximum operation frequency than single slope operation. However, due to the sym-
metric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP.
When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal
to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on
illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM out-
puts. The small horizontal line marks on the TCNT0 slopes represent Compare Matches
between OCR0x and TCNT0.
Figure 13-7. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to
Figure 13-7 on page
TCNTn
OCn
OCn
Period
81. The TCNT0 value is in the timing diagram shown as a histogram for
1
2
3
ATtiny24/44/84
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
(COMnx1:0 = 2)
(COMnx1:0 = 3)
81
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