WM8580AGEFTRV WOLFSON [Wolfson Microelectronics plc], WM8580AGEFTRV Datasheet - Page 24
WM8580AGEFTRV
Manufacturer Part Number
WM8580AGEFTRV
Description
Multichannel CODEC with S/PDIF Transceiver
Manufacturer
WOLFSON [Wolfson Microelectronics plc]
Datasheet
1.WM8580AGEFTRV.pdf
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WM8580
AUDIO DATA FORMATS
w
Table 15 Master Mode BCLK Control
Five popular interface formats are supported:
•
•
•
•
•
All five formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the
exception of 32 bit right justified mode, which is not supported.
Audio Data for each stereo channel is time multiplexed with the interface’s Left-Right-Clock (LRCLK),
indicating whether the left or right channel is present. The LRCLK is also used as a timing reference
to indicate the beginning or end of the data words.
In Left Justified, Right Justified and I
2 times the selected word length. LRCLK must be high for a minimum of BCLK periods equivalent to
the audio word length, and low for minimum of the same number of BCLK periods. Any mark to
space ratio on LRCLK is acceptable provided these requirements are met.
REGISTER
ADDRESS
Left Justified mode
Right Justified mode
I
DSP Mode A
DSP Mode B
PAIF 1
PAIF 2
SAIF 1
2
S mode
R10
R11
09h
0Ah
0Bh
R9
4:3
4:3
4:3
BIT
PAIFRX_BCLKSEL
PAIFTX_BCLKSEL
SAIF_BCLKSEL
LABEL
2
[1:0]
[1:0]
[1:0]
S modes, the minimum number of BCLKs per LRCLK period is
DEFAULT
00
00
00
Master Mode BCLK Rate:
00 = 64 BCLKs per LRCLK
01 = 32 BCLKs per LRCLK
10 = 16 BCLKs per LRCLK
11 = BCLK = System Clock.
DESCRIPTION
PD Rev 4.3 August 2007
Production Data
24
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