ISPPACCLK5610AV-01T100C LATTICE [Lattice Semiconductor], ISPPACCLK5610AV-01T100C Datasheet
ISPPACCLK5610AV-01T100C
Related parts for ISPPACCLK5610AV-01T100C
ISPPACCLK5610AV-01T100C Summary of contents
Page 1
June 2008 Features ■ 8MHz to 400MHz Input/Output Operation ■ Low Output to Output Skew (<50ps) ■ Low Jitter Peak-to-Peak ■ Programmable Fan-out Buffers • Programmable output standards and individual enable controls - LVTTL, LVCMOS, HSTL, eHSTL, ...
Page 2
Lattice Semiconductor General Description and Overview The ispClock5610A and ispClock5620A are in-system-programmable high-fanout enhanced zero delay clock gen- erators designed for use in high performance communications and computing applications. The ispClock5610A provides single-ended or five differential clock ...
Page 3
Lattice Semiconductor Figure 1-2. ispClock5620A Functional Block Diagram PS0 PS1 Profile Select Control REFSEL REFA+ INPUT REFA- DIVIDER 0 M REFVTT (1-40) 1 REFB+ REFB- FEEDBACK N DIVIDER (1-40) FBKSEL FBKA FBKA- 0 FBKVTT ...
Page 4
Lattice Semiconductor Absolute Maximum Ratings Core Supply Voltage -0.5 to 5.5V CCD PLL Supply Voltage ...
Page 5
Lattice Semiconductor 2 E CMOS Memory Write/Erase Characteristics Parameter Erase/Reprogram Cycles Performance Characteristics – Power Supply Symbol Parameter 3 I Core Supply Current CCD 3 I Analog Supply Current CCA Output Driver Supply Current I CCO (per Bank) I JTAG ...
Page 6
Lattice Semiconductor DC Electrical Characteristics – LVDS Symbol Parameter V Common Mode Input Voltage ICM V Differential Input Threshold THD V Input Voltage IN V Output High Voltage OH V Output Low Voltage OL V Output Voltage Differential OD ΔV ...
Page 7
Lattice Semiconductor Electrical Characteristics – Differential SSTL2 Symbol Parameter V Output Supply Voltage CCO V DC Differential Input Voltage Swing SWING(DC Input Differential Voltage SWING(AC) Input Pair Differential Crosspoint V IX Voltage TCKD Clock Duty Cycle Electrical Characteristics ...
Page 8
Lattice Semiconductor Switching Characteristics – Timing Adders for I/O Modes Adder Type 2 t Input Adders IOI LVTTL_in Using LVTTL Standard LVCMOS18_in Using LVCMOS 1.8V Standard LVCMOS25_in Using LVCMOS 2.5V Standard LVCMOS33_in Using LVCMOS 3.3V Standard SSTL18_in Using SSTL18 Standard ...
Page 9
Lattice Semiconductor Output Rise and Fall Times – Typical Values Slew 1 (Fastest) Output Type LVTTL 0.54 0.76 LVCMOS 1.8V 0.75 0.69 LVCMOS 2.5V 0.57 0.69 LVCMOS 3.3V 0.55 0.77 SSTL18 0.55 0.40 SSTL2 0.50 0.40 ...
Page 10
Lattice Semiconductor Figure 1-5. LVDS/LVPECL Termination Load 50Ω/3" 50Ω/1" ispCLOCK 50Ω/3" 50Ω/1" Figure 1-6. Differential HSTL/SSTL Termination Load ispCLOCK Interface Circuit 3pF (parasitic) 0.1U 34Ω 33.2Ω 44.2Ω 0.1U 33.2Ω 34Ω 3pF (parasitic) 50Ω/3" 50Ω/1" 50Ω VTERM 50Ω/3" 50Ω/1" 50Ω 1-10 ...
Page 11
Lattice Semiconductor Programmable Input and Output Termination Characteristics Symbol Parameter R Input Resistance Output Resistance OUT 1. Guaranteed by characterization. Conditions V Voltage CCO Rin=40Ω setting Rin=45Ω setting Rin=50Ω setting Rin=55Ω setting Rin=60Ω setting Rin=65Ω setting Rin=70Ω ...
Page 12
Lattice Semiconductor Performance Characteristics – PLL Symbol Parameter Reference and feedback input f f REF, FBK frequency range t Reference and feedback input CLOCKHI, t clock HIGH and LOW times CLOCKLO t Reference and feedback input RINP, t rise and ...
Page 13
Lattice Semiconductor Timing Specifications Skew Matching Symbol Parameter Between any two identically configured and loaded t Output-output Skew SKEW outputs regardless of bank. Programmable Skew Control Symbol Parameter t Skew Control Range SKRANGE SK Skew Steps per range STEPS 2 ...
Page 14
Lattice Semiconductor Timing Specifications (Cont.) Boundary Scan Logic Symbol t TCK (BSCAN Test) Clock Cycle BTCP t TCK (BSCAN Test) Pulse Width High BTCH t TCK (BSCAN Test) Pulse Width Low BTCL t TCK (BSCAN Test) Setup Time BTSU t ...
Page 15
Lattice Semiconductor Timing Diagrams Figure 1-8. Erase (User Erase or Erase All) Timing Diagram VIH TMS VIL SU1 SU1 CKH GKL VIH TCK VIL State Update-IR Run-Test/Idle (Erase) Figure 1-9. Programming Timing Diagram VIH ...
Page 16
Lattice Semiconductor Typical Performance Characteristics I vs. f CCD (Normalized to 800MHz) 1.2 1 0.8 0.6 0.4 0.2 0 300 400 500 f (MHz) VCO Typical Skew Error vs. Setting (Skew Mode = FINE ...
Page 17
Lattice Semiconductor Typical Performance Characteristics (Cont.) Typical Phase Jitter vs. VCO Frequency PFD MHz 16 320 370 420 470 VCO Frequency Typical Period Jitter vs. VCO ...
Page 18
Lattice Semiconductor Lock Detect mode. In Phase Lock Detect mode, the LOCK signal is asserted if the phases of the reference and feedback signals match, whereas in Frequency Lock Detect mode the LOCK signal is asserted when the frequen- cies ...
Page 19
Lattice Semiconductor The input, or M-Divider prescales the input reference frequency, and can be programmed with integer values over the range 40. To achieve low levels of output jitter best to use the smallest M-Divider ...
Page 20
Lattice Semiconductor Note: Bypassing M- and N-Dividers also results in reducing the number of output frequency combinations gener- ated from a single reference clock input. PLL_BYPASS Mode The PLL_BYPASS mode is provided so that input reference signals can be coupled ...
Page 21
Lattice Semiconductor Figure 1-14. ispClock5600A Clock Reference and Feedback Input Structure (REFA+/- Pair Shown) ispClock5600A REFA+ REFA- REFVTT The following usage guidelines are suggested for interfacing to supported logic families. LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V) The receiver should be ...
Page 22
Lattice Semiconductor pairs is not used, tie the unused pins REF+ and REF- to GND. In addition, if external feedback is not used, tied FBVTT to GND. One important point to note is that the termination supplies must have low ...
Page 23
Lattice Semiconductor LVDS/Differential LVPECL The receiver should be set to LVDS or LVPECL mode as required and both termination resistors should be engaged and set to 50Ω. The associated REFVTT or FBKVTT pin, however, should be left unconnected. This cre- ...
Page 24
Lattice Semiconductor actual impedance required will be a function of the driver used to generate the signal and the transmission medium used (PCB traces, connectors and cabling). The ispClock5600A’s ability to adjust input impedance over a range of 40Ω to ...
Page 25
Lattice Semiconductor Figure 1-20. ispClock5600A Output Driver and Skew Control OEX OEY GOE V-Dividers 2 E CMOS 2 E CMOS OEX OEY GOE From V-Dividers 2 E CMOS On / Off Skew Adjust From Skew Adjust On / Off 2 ...
Page 26
Lattice Semiconductor Each of the ispClock5600A’s output driver banks can be configured to support the following logic outputs: • LVTTL • LVCMOS (1.8V, 2.5V, 3.3V) • SSTL2 • SSTL3 • HSTL • eHSTL • LVDS • Differential LVPECL (3.3V) • ...
Page 27
Lattice Semiconductor Figure 1-22 shows a typical configuration for the ispClock5600A’s output driver when configured to drive SSTL2, SSTL3, HSTL or eHSTL loads. The ispClock5600A’s output impedance should be set to 40Ω for driving SSTL2 or SSTL3 loads and to ...
Page 28
Lattice Semiconductor When GOE is HIGH, all output drivers are forced into a high-Z state, regardless of any internal configuration. When GOE is LOW, the output drivers may also be enabled or disabled on an individual basis, and optionally controlled ...
Page 29
Lattice Semiconductor For fine skew mode, When an output driver is programmed to support a differential output mode, a single skew setting is applied to both the BANKxA+ and BANKxB- signals. When the output driver is configured to support a ...
Page 30
Lattice Semiconductor coarse mode has a value greater than 40, as the corresponding fine skew mode setting would be greater than 80, which is not supported. Output Skew Matching and Accuracy Understanding the various factors which relate to output skew ...
Page 31
Lattice Semiconductor Figure 1-26. Output Timing Adders for Logic Type (a) and Output Slew Rate (b) LVDS Output ( IOO LVTTL Output (T = 0.395ns) IOO (a) Similarly, when one changes the slew rate of an output, the ...
Page 32
Lattice Semiconductor Internal Feedback Mode In addition to supporting the use of external feedback to close the phase-locked loop, ispClock5620A also provides the option of using an internal feedback path for this function. This feature is useful for minimizing external ...
Page 33
Lattice Semiconductor RESET and Power-up Functions To ensure proper PLL startup and synchronization of outputs, the ispClock5600A provides both internally gener- ated and user-controllable external reset signals. An internal reset is generated whenever the device is powered up. An external ...
Page 34
Lattice Semiconductor Figure 1-28. Maximum Ambient Temperature vs. Number of Active Output Banks Temperature Derating Curves (Outputs LVCMOS33 3.3V Active Output Banks 5620A Industrial 5620A Commercial 5610A ...
Page 35
Lattice Semiconductor Figure 1-29. PAC-Designer Design Entry Screen In-System Programming The ispClock5600A is an In-System Programmable (ISP™) device. This is accomplished by integrating all 2 E CMOS configuration control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant ...
Page 36
Lattice Semiconductor Evaluation Fixture Included in the basic ispClock5600A Design Kit is an engineering prototype board that can be connected to the parallel port using a Lattice ispDOWNLOAD ispClock5600A and can be used in real time to ...
Page 37
Lattice Semiconductor Figure 1-31. ispClock5600A TAP Registers TDI TAP Controller Specifics The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether an Instruction Register or Data Register operation is performed. Driven ...
Page 38
Lattice Semiconductor Figure 1-32. TAP States Test-Logic-Rst Run-Test/Idle Note: The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. When the ...
Page 39
Lattice Semiconductor For ispClock5600A, the instruction word length is eight bits. All ispClock5600A instructions available to users are shown in Table 1-6. The following table lists the instructions supported by the ispClock5600A JTAG Test Access Port (TAP) controller: Table 1-6. ...
Page 40
Lattice Semiconductor Figure 1-33. ispClock5600A Family ID Codes Version (4 bits Configured Version (4 bits Configured In addition to the four instructions described above, there are 20 unique instructions specified by Lattice for the ispClock5600A. These ...
Page 41
Lattice Semiconductor VERIFY_INCR – This instruction copies the E umn register and then auto-increments the value of the address register. The device must already be in program- ming mode for this instruction to execute. DISCHARGE – This instruction is used ...
Page 42
Lattice Semiconductor Pin Descriptions Pin Name Description VCCO_0 Output Driver ‘0’ VCC VCCO_1 Output Driver ‘1’ VCC VCCO_2 Output Driver ‘2’ VCC VCCO_3 Output Driver ‘3’ VCC VCCO_4 Output Driver ‘4’ VCC VCCO_5 Output Driver ‘5’ VCC VCCO_6 Output Driver ...
Page 43
Lattice Semiconductor Pin Descriptions (Continued) Pin Name Description VCCD Digital Core VCC GNDD Digital GND VCCJ JTAG interface VCC REFA+ Clock Reference A positive input REFA- Clock Reference A negative input REFB+ Clock Reference B positive input REFB- Clock Reference ...
Page 44
Lattice Semiconductor Detailed Pin Descriptions VCCO_[0..9], GNDO_[0..9] – These pins provide power and ground for each of the output banks. In the case when an output bank is unused, its corresponding VCCO pin may be left unconnected or preferably should ...
Page 45
Lattice Semiconductor GOE – Global output enable. This pin drives all outputs to a high-impedance state when it is pulled HIGH. GOE also controls the internal feedback buffer, so that bringing GOE high will cause the PLL to lose lock. ...
Page 46
Lattice Semiconductor Package Diagrams 48-Pin TQFP (Dimensions in Millimeters) PIN 1 INDICATOR 0. SECTION NOTES: 1. ...
Page 47
Lattice Semiconductor 100-Pin TQFP (Dimensions in Millimeters) PIN 1 INDICATOR TOP VIEW SECTION B-B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982. 2. ALL ...
Page 48
Lattice Semiconductor Part Number Description ispPAC-CLK56XXA XXXX X Device Family Device Number CLK5610A CLK5620A Ordering Information Conventional Packaging Part Number ispPAC-CLK5610AV-01T48C ispPAC-CLK5620AV-01T100C Part Number ispPAC-CLK5610AV-01T48I ispPAC-CLK5620AV-01T100I Lead-Free Packaging Part Number ispPAC-CLK5610AV-01TN48C ispPAC-CLK5620AV-01TN100C Part Number ispPAC-CLK5610AV-01TN48I ispPAC-CLK5620AV-01TN100I Commercial ...
Page 49
Lattice Semiconductor Package Options ispClock5610A: 48-pin TQFP VCCO_0 BANK_0B BANK_0A GNDO_0 VCCO_1 BANK_1B BANK_1A GNDO_1 VCCO_2 BANK_2B BANK_2A GNDO_2 ispClock5600A Family Data Sheet ispPAC CLK5610AV-01T48C 1-49 36 VCCJ ...
Page 50
Lattice Semiconductor ispClock5620A: 100-pin TQFP n/c 1 n/c 2 VCCO_0 3 BANK_0B 4 BANK_0A 5 GNDO_0 6 VCCO_1 7 BANK_1B 8 BANK_1A 9 GNDO_1 10 VCCO_2 11 BANK_2B 12 BANK_2A 13 GNDO_2 14 VCCO_3 15 BANK_3B 16 BANK_3A 17 GNDO_3 ...
Page 51
Lattice Semiconductor Revision History Date Version — — March 2007 01.3 June 2008 01.4 Change Summary Previous Lattice releases. Added min. and max. values to Timing Adders for I/O Modes table. Added min. and max. values to PLL Bypass Mode ...