ISPPACCLK5610AV-01T100C LATTICE [Lattice Semiconductor], ISPPACCLK5610AV-01T100C Datasheet - Page 37

• Manufacturer Part Number: ISPPACCLK5610AV-01T100C
• Description: In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Figure 1-31. ispClock5600A TAP Registers
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether
an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a
small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as
shown in Figure 1-32. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO)
becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run-
Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But
there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a
reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on
default state.
TDI
TEST ACCESS PORT (TAP)
INSTRUCTION REGISTER (8 BITS)
ADDRESS REGISTER (10 BITS)
TCK
IDCODE REGISTER (32 BITS)
B-SCAN REGISTER (56 BITS)
BYPASS REGISTER (1 BIT)
DATA REGISTER (97 BITS)
UES REGISTER (32 BITS)
LOGIC
TMS
1-37
OUTPUT
LATCH
TDO
ispClock5600A Family Data Sheet
NON-VOLATILE
MEMORY
E
2
CMOS