F25L32QA-100PAG ESMT [Elite Semiconductor Memory Technology Inc.], F25L32QA-100PAG Datasheet - Page 11

• Manufacturer Part Number: F25L32QA-100PAG
• Description: 3V Only 32 Mbit Serial Flash Memory with Dual and Quad
• Manufacturer: ESMT [Elite Semiconductor Memory Technology Inc.]

ESMT
SPI flash memory without resetting the clocking sequence. To
activate the HOLD mode, CE must be in active low state. The
with the falling edge of the HOLD signal. The HOLD mode ends
when the HOLD signal’s rising edge coincides with the SCK
active low state.
If the falling edge of the HOLD signal does not coincide with the
SCK active low state, then the device enters Hold mode when the
SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD signal does not
coincide with the SCK active low state, then the device exits in
Hold mode when the SCK next reaches the active low state. See
Figure 1 for Hold Condition waveform.
F25L32QA provides software Write Protection.
The Write-Protect pin ( WP ) enables or disables the lock-down
function of the status register. The Block-Protection bits (BP2,
BP1, BP0, and BPL) in the status register provide Write
protection to the memory array and the status register. When the
QE bit of Status Register-2 is set for Quad I/O, the WP pin
function is not available since this pin is used for SIO
4 for Block-Protection description.
Write Protect Pin (
The Write-Protect ( WP ) pin enables the lock-down function of
the BPL bit (bit 7) in the status register. When WP is driven low,
the execution of the Write Status Register (WRSR) instruction is
determined by the value of the BPL bit (see Table 4). When WP
is high, the lock-down function of the BPL bit is disabled.
Elite Semiconductor Memory Technology Inc.
HOLD pin is used to pause a serial sequence underway with the
HOLD mode begins when the SCK active low state coincides
HOLD OPERATION
WRITE PROTECTION
Figure 1: HOLD Condition Waveform
HO L D
S CK
WP
)
A ctive
(Preliminary)
2
. See Table
Ho ld
Once the device enters Hold mode, SO will be in high impedance
state while SI and SCK can be V
If CE is driven active high during a Hold condition, it resets the
internal logic of the device. As long as HOLD signal is low, the
memory
communication with the device, HOLD must be driven active
high, and CE must be driven active low. See Figure 23 for Hold
timing.
The HOLD function is only available for Standard SPI and Dual
SPI operation, not during Quad SPI because this pin is used for
SIO
Table 4: Conditions to Execute Write-Status- Register
3
WP
H
L
L
when the QE bit of Status Register-2 is set for Quad I/O.
A ctive
(WRSR) Instruction
remains
BPL
X
1
0
Execute WRSR Instruction
in
Ho ld
Publication Date: Jan. 2009
Revision: 0.2
the
Not Allowed
Allowed
Allowed
Hold
IL
or V
IH
condition.
.
F25L32QA
A ctive
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To
resume