F25L32QA-100PAG ESMT [Elite Semiconductor Memory Technology Inc.], F25L32QA-100PAG Datasheet - Page 12

• Manufacturer Part Number: F25L32QA-100PAG
• Description: 3V Only 32 Mbit Serial Flash Memory with Dual and Quad
• Manufacturer: ESMT [Elite Semiconductor Memory Technology Inc.]

ESMT
INSTRUCTIONS
Instructions are used to Read, Write (Erase and Program), and
configure the F25L32QA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Page Program, Auto Address Increment (AAI)
Programming, Write Status Register, Sector Erase, Block Erase,
or Chip Erase instructions, the Write Enable (WREN) instruction
must be executed first. The complete list of the instructions is
provided in Table 5. All instructions are synchronized off a high to
low transition of CE . Inputs will be accepted on the rising edge
of SCK starting with the most significant bit. CE must be driven
Operation
Read
Fast Read
Fast Read Dual Output
Fast Read Dual I/O
Fast Read Quad
Output
Fast Read Quad I/O
Sector Erase
Block Erase
Chip Erase
Page Program (PP)
Quad Page Program
Auto Address Increment
word programming
Mode Bit Reset
Deep Power Down (DP)
Read Status Register-1
(RDSR-1)
Read Status Register-2
(RDSR-2)
Enable Write Status
Register (EWSR)
Write Status Register
(WRSR)
Write Enable (WREN)
Write Disable (WRDI)/ Exit
secured OTP mode
Enter secured OTP mode
(ENSO)
Release from Deep Power
Down (RDP)
Read Electronic Signature
(RES)
RES in secured OTP mode
& not lock down
RES in secured OTP mode
& lock down
Elite Semiconductor Memory Technology Inc.
8
12, 15
7
6
6
4,
4
(64K Byte)
(4K Byte)
18
7
5
12, 14
12, 16
(AAI)
17
10
12,13
100
33
50
Max.
Freq
MHz
~
MHz
MHz
B1H
60H /
C7H
02H
05H
35H
50H
01H
06H
04H
B9h
ADH Hi-Z A
ABH Hi-Z
ABH Hi-Z
ABH Hi-Z
ABH Hi-Z
0BH
D8H
FFH
03H
20H
S
IN
BBH
EBH
3BH
6BH
32H
1
S
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z
Hi-Z A
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Table 5: Device Operation Instruction
OUT
(S
(Preliminary)
A
FFH
23
23
23
23
23
23
D
S
7
X
X
X
X
X
23
-
-
-
-
-A
-A
-A
-A
-
-A
-A
-
-
-S
IN
IN
A
A
A
-A
A
16
16
16
16
16
16
0
23
23
23
)
23
0,
2
-A
-A
-A
-A
M
(S
(S
16
16
16
S
D
D
Hi-Z
Hi-Z
8
7
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
15
-M
7
OUT
OUT
OUT
X
X
X
-
-
-S
-
-
-
-
-
-S
0
0
8
)
)
(S
A
A
A
A
A
A
A
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read ID, Read Status Register, Read Electronic Signature
instructions). Any low to high transition on CE , before receiving
the last bit of an instruction bus cycle, will terminate the
instruction in progress and return the device to the standby
mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
X, D
15
15
15
15
15
15
D
15
S
7
X
X
X
-A
-
-
-
-
-
-
-
-
-
-
IN
-A
-A
-A
-A
-A
-A
IN
-S
A
A
A
15
0,
15
15
8
8
8
8
8
8
8
OUT0~1
3
)
-A
M
-A
-A
7
S
8
8
8
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z
-M
OUT
X
X
X
-
-
-
-
-
-
-
-
-
-
Bus Cycle
0
S
7
7
7
7
7
7
-.
-.
X
X
X
-A
-A
-A
-A
-
-A
-A
-
-
-
-
-
-
-
-
D
D
IN
A
A
A
OUT0~1
OUT2~6
0
0
0
0
0
0
7
7
7
4
-A
-A
-A
1~3
S
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
0
OUT
X
X
X
-
-
-
-
-
-
-
-
-
-
-
Publication Date: Jan. 2009
Revision: 0.2
D
D
S
X
X
X
X
X
-
-
-
IN0
IN0
-
-
-
-
-
-
-
-
-
-
IN
D
cont.
cont.
IN0~3
X
X
5
D
S
Hi-Z
Hi-Z
15H
35H
75H
OUT0
OUT
X
-
-
-
-
-
-
-
-
-
-
-
-
-
F25L32QA
D
D
S
X
X
D
D
-
-
-
IN1
IN1
-
-
-
-
-
-
-
-
-
-
-
-
-
IN
D
OUT0~1
OUT0~3
IN4~7
6
-
-
D
D
S
Hi-Z
Hi-Z
OUT1
OUT0
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12/42
Up to
bytes
256
S
Up to 256
X
X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IN
cont.
cont.
bytes
N
-
-
cont.
cont.
S
Hi-Z
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-