F25L32QA-100PAG ESMT [Elite Semiconductor Memory Technology Inc.], F25L32QA-100PAG Datasheet - Page 28

• Manufacturer Part Number: F25L32QA-100PAG
• Description: 3V Only 32 Mbit Serial Flash Memory with Dual and Quad
• Manufacturer: ESMT [Elite Semiconductor Memory Technology Inc.]

ESMT
Write-Status-Register (WRSR)
The Write Status Register instruction writes new values to the
BP2, BP1, BP0, BPL (Status Register-1) and QE (Status
Register-2) bits of the status register. CE must be driven low
before the command sequence of the WRSR instruction is
entered and driven high before the WRSR instruction is executed.
that is clocked in. If it is not done, the WRSR instruction will not
be issued. If CE is high after the eighth bits of data, the QE bit
will be cleared to 0. See Figure 23 for EWSR or WREN and
WRSR instruction sequences.
Executing the Write Status Register instruction will be ignored
when WP is low and BPL bit is set to “1”. When the WP is
low, the BPL bit can only be set from “0” to “1” to lock down the
Enter OTP Mode (ENSO)
The ENSO (B1H) instruction is for entering the additional 2K
bytes secured OTP mode. The additional 2K bytes secured OTP
sector is independent from main array, which may use to store
unique serial number for system identifier. User must unprotect
whole array (BP0=BP1=BP2=0), prior to any Write (Program/
Erase) operation in OTP sector. After entering the secured OTP
mode, only the secured OTP sector can be accessed and user
Elite Semiconductor Memory Technology Inc.
CE must be driven high after the eighth or sixteenth bit of data
Figure 23: Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Status-Register (WRSR)
Figure 24: Enter OTP Mode (ENSO) Sequence
SI
SCK
SO
CE
MODE3
MODE0
MSB
0 1 2 3 4 5 6 7
50 or 06
(Preliminary)
HIGH IMPENANCE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 151617 1819 20 21 22 23
status register, but cannot be reset from “1” to “0”.
When WP is high, the lock-down function of the BPL bit is
disabled and the BPL, BP0, BP1,and BP2 bits in the status
register can all be changed. As long as BPL bit is set to 0 or WP
pin is driven high (V
register can all be altered by the WRSR instruction. In this case,
a single WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0; BP1 and BP2 bits
at the same time. See Table 4 for a summary description of WP
and BPL functions.
can follow the standard Read or Write procedure except for Block
Erase and Chip Erase. The secured OTP data cannot be
updated again once it is lock down. In secured OTP mode,
WRSR command will ignore the input data and lock down the
secured OTP sector (OTP_lock bit =1). To exit secured OTP
mode, user must execute WRDI command. RES can be used to
verify the secured OTP status as shown in Table 6.
CE pin at the end of the WRSR instruction, the bits in the status
01
MSB
7 6 5 4 3 2 1 0 15 14 13 12
Stauts Register - 1
Data In
IH
) prior to the low-to-high transition of the
Publication Date: Jan. 2009
Revision: 0.2
Stauts Register - 2
Data In
1110
F25L32QA
9 8
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