ADV601JS Analog Devices, ADV601JS Datasheet - Page 47

• Manufacturer Part Number: ADV601JS
• Description: Low Cost Multiformat Video Codec
• Manufacturer: Analog Devices

Host Interface (Compressed Data) Register Timing
The diagrams in this section show transfer timing for host read and write transfers to the ADV601’s Compressed Data register. Ac-
cesses to the Compressed Data register are faster than access timing for the Indirect Address, Indirect Register Data, and Interrupt
Mask/Status registers. For information on access timing for the other registers, see the Host Interface (Indirect Address, Indirect
Register Data, and Interrupt Mask/Status) Register Timing section. Also note that as long as your system observes the RD or WR
signal assertion timing, your system does NOT have to wait for the ACK signal between new compressed data addresses.
Parameter
t
t
t
t
t
t
t
t
t
REV. 0
RD_CD_RDC
RD_CD_PWA
RD_CD_PWD
ADR_CD_RDS
ADR_CD_RDH
DATA_CD_RDD
DATA_CD_RDOH
ACK_CD_RDD
ACK_CD_RDOH
(I) ADR, BE, CS
(O) DATA
(O) ACK
(I) RD
Description
RD Signal, Compressed Data Direct Register, Read Cycle Time
RD Signal, Compressed Data Direct Register, Pulse Width Asserted
RD Signal, Compressed Data Direct Register, Pulse Width Deasserted
ADR Bus, Compressed Data Direct Register, Read Setup
ADR Bus, Compressed Data Direct Register, Read Hold (at 27 MHz VCLK)
DATA Bus, Compressed Data Direct Register, Read Delay
DATA Bus, Compressed Data Direct Register, Read Output Hold
ACK Signal, Compressed Data Direct Register, Read Delay
ACK Signal, Compressed Data Direct Register, Read Output Hold
Table XXXV. Host (Compressed Data) Read Timing Parameters
Figure 39. Host (Compressed Data) Read Transfer Timing
t
ADR_CD_RDS
t
RD_CD_PWA
VALID
VALID
t
RD_CD_RDC
t
ACK_CD_RDOH
t
t
t
DATA_CD_RDOH
RD_CD_PWD
–47–
ADR_CD_RDH
t
VALID
DATA_CD_RDD
t
ACK_CD_RDD
VALID
Min
28
10
10
2
2
N/A
18
N/A
9
ADV601
Max
N/A
N/A
N/A
N/A
N/A
10
N/A
18
N/A
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns