M30622 Mitsubishi, M30622 Datasheet - Page 128

• Manufacturer Part Number: M30622
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Manufacturer: Mitsubishi

Clock asynchronous serial I/O (UART) mode
Table 1.19.5. Specifications of UART Mode (1)
Note 1: ‘n’ denotes the value 00
Note 2: f
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
Note 4: In M30623(80-pin package), do not use these functions, because there is no external pin of CTS
(2) Clock asynchronous serial I/O (UART) mode
Transfer data format
Transfer clock
Transmission/reception control
Transmission start condition • To start transmission, the following requirements must be met:
Reception start condition
Interrupt request
generation timing
Error detection
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 1.19.5 and 1.19.6 list the specifications of the UART mode. Figure 1.19.15 shows
the UARTi transmit/receive mode register.
Tentative Specifications REV.A
because there is no external pin of CLK
EXT
the UARTi receive interrupt request bit is not set to “1”.
S
Item
pecifications in this manual are tentative and subject to change.
is input from the CLKi pin. In M30623(80-pin package), do not select the external clock as transfer clock,
16
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
• When internal clock is selected (bit 3 at addresses 03A0
• When external clock is selected (bit 3 at addresses 03A0
• CTS function/RTS function/CTS, RTS function chosen to be invalid (Note 4)
- Transmit enable bit (bit 0 at addresses 03A5
- Transmit buffer empty flag (bit 1 at addresses 03A5
- When CTS function selected, CTS input level = “L” (Note 4)
• To start reception, the following requirements must be met:
• When transmitting
-
- Transmit interrupt cause select bits (bits 0, 1 at address 03B0
•
- Interrupts requested when data transfer from UARTi receive register to
• Overrun error (Note 3)
• Framing error
• Parity error
• Error sum flag
- Receive enable bit (bit 2 at addresses 03A5
- Start bit detection
When receiving
f
T
address 037D
transfer buffer register to UARTi transmit register is completed
address 037D
UARTi transfer register is completed
UARTi receive buffer register is completed
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
This error occurs when the number of stop bits set is not detected
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
_______
EXT
fi/16(n+1) (Note 1) fi = f
to FF
ransmit interrupt cause select bits (bits 0,1 at address 03B0
/16(n+1) (Note 1) (Note 2)
16
_______
that is set to the UARTi bit rate generator.
2
_______
16
16
.
) = “0”: Interrupts requested when data transfer from UARTi
) = “1”: Interrupts requested when data transmission from
128
1
, f
_______
8
Specification
, f
_______
32
_______
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
16
16
, 03AD
, 03AD
16
16
16
, 03AD
, 03A8
Mitsubishi microcomputers
, 03A8
16
16
, 037D
, 037D
M16C / 62T Group
16
16
16
________ ________
, 0378
, 037D
, 0378
16
16
16
16
, bit4 at
, bit4 at
2
) = “1”
) = “1”
/RTS
16
16
16
= “0”) :
=“1”) :
) = “0”
2
.